Xilinx Spartan-3E 1600E VGA Signal Timing

56 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide

www.xilinx.com UG257 (v1.1) December 5, 2007

Chapter 6: VGA Dis play Port R

display is redrawn. The minimum refresh frequency is a function of the display’s phosphor

and electron beam intensity, with practical refresh frequencies in the 60Hz to 120 Hz

range. The number of horizontal lines displayed at a given refresh frequency defines the

horizontal retrace frequency.

VGA Signal Timing

The signal timings in Table6-2 are derived for a 640-pixel by 480-row display using a

25 MHz pixel clock and 60 Hz ± 1 refresh. Figure 6-3 shows the relation between each of

the timing symbols. The timing for the sync pulse width (TPW) and front and back porch

intervals (TFP and TBP) are based on observations from various VGA displays. The front

and back porch intervals are the pre- and post-sync pulse times. Information cannot be

displayed during these times.

Generally, a counter clocked by the pixel clock controls the horizontal timing. Decoded

counter values generate the HS signal. This counter tracks the current pixel display

location on a given row.

A separate counter tracks the vertical timing. The vertical-sync counter increments with

each HS pulse and decoded values generate the VS signal. This counter tracks the current

display row. These two continuously running counters form the address into a video

display buffer. For example, the on-board DDR SDRAM provides an ideal display buffer.

No time relationship is specified between the onset of the HS pulse and the onset of the VS

pulse. Consequently, the counters can be arranged to easily form video RAM addresses, or

to minimize decoding logic for sync pulse generation.

Tabl e 6 - 2 : 640x480 Mode VGA Timing

Symbol Parameter Vertical Sync Horizontal Sync

Time Clocks Lines Time Clocks

TS Sync pulse time 16.7 ms 416,800 521 32 µs 800

TDISP Display time 15.36 ms 384,000 480 25.6 µs 640

TPW Pulse width 64 µs 1,600 2 3.84 µs 96

TFP Front porch 320 µs 8,000 10 640 ns 16

TBP Back porch 928 µs 23,200 29 1.92 µs 48

Figure 6-3: VGA Con trol Timin g

UG257_06_03_060506

TS

Tdisp

Tfp

Tbp

Tpw

Contents

Main Revision History The following table shows the revision history for this document. Table of Contents Preface: About This Guide Chapter 1: Introduction and Overview Chapter 2: Switches, Buttons, and Knob Chapter 3: Clock Sources Chapter 4: FPGA Configuration Options Chapter 5: Character LCD Screen Chapter 6: VGA Display Port Chapter 7: RS-232 Serial Ports Chapter 8: PS/2 Mouse/Keyboard Port Chapter 9: Digital to Analog Converter (DAC) Chapter 10: Analog Capture Circuit Chapter 11: Intel StrataFlash Parallel NOR Flash PROM Chapter 12: SPI Serial Flash Chapter 13: DDR SDRAM Chapter 14: 10/100 Ethernet Physical Layer Interface Chapter 15: Expansion Connectors Chapter 16: XC2C64A CoolRunner-II CPLD Chapter 17: DS2432 1-Wire SHA-1 EEPROM Appendix A: Schematics Appendix B: Example User Constraints File (UCF) Page Preface About This Guide Acknowledgements Guide Contents Additional Resources Chapter 1 Introduction and Overview Choose the Starter Kit Board for Your Needs Spartan-3E FPGA Features and Embedded Processing Functions Learning Xilinx FPGA, CPLD, and ISE Development Software Basics Advanced Spartan-3 Generation Development Boards Key Components and Features Design Trade-Offs Configuration Methods Galore! Voltages for all Applications Page Chapter 2 Switches, Buttons, and Knob Slide Switches Push-Button Switches Rotary Push-Button Switch Push-Button Switch Rotary Shaft Encoder GND Vcco Vcco B=1 A=0 Discrete LEDs A B Page Chapter 3 Clock Sources Clock Connections Vol tag e Co nt ro l 50 MHz On-Board Oscillator Auxiliary Clock Oscillator Socket SMA Clock Input or Output Connector Location Clock Period Constraints Page Chapter 4 FPGA Configuration Options 24 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide Chapter 4: FPGA Configuration Options R Figure 4-1: MicroBlaze Development Kit Board FPGA Configuration Options Figure 4-2: Detailed Configuration Options Spartan-3E Development Board Configuration Mode Jumpers PROG Push Button DONE Pin LED Programming the FPGA, CPLD, or Platform Flash PROM via USB Connecting the USB Cable USB Type B Connector USB Type A Connector Programming via iMPACT Page Programming Platform Flash PROM via USB Generating the FPGA Configuration Bitstream File Page Generating the PROM File Page Page Page Page Programming the Platform Flash PROM Page Page Page Chapter 5 Character LCD Screen Figure 5-1: Character LCD Interface Spartan-3E FPGA LCD Header (J13) Character LCD Interface Signals Voltage Compatibility Interaction with Intel StrataFlash LCD Controller Memory Map DD RAM CG ROM CG RAM Command Set Disabled Clear Display Bit DB1: (I/D) Increment/Decrement Return Cursor Home Entry Mode Set Display On/Off Bit DB2: (D) Display On/Off Bit DB1: (C) Cursor On/Off Bit DB0: (B) Cursor Blink On/Off Cursor and Display Shift Function Set Set CG RAM Address Set DD RAM Address Read Busy Flag and Address Write Data to CG RAM or DD RAM Operation Four-Bit Data Interface Transferring 8-Bit Data over the 4-Bit Interface Initializing the Display Power-On Initialization Display Configuration Writing Data to the Display Disabling the Unused LCD Chapter 6 VGA Display Port n Figure 6-1: VGA Con nect ions from Spart an-3 E Sta rter Kit Board 9 Pin 1 Pin 6 Pin 11 Signal Timing for a 60 Hz, 640x480 VGA Display Page VGA Signal Timing Page Page Chapter 7 RS-232 Serial Ports Chapter 7: RS-232 Serial Ports R Figure 7-1: RS-232 Serial Ports OR Page Page Chapter 8 PS/2 Mouse/Keyboard Port Keyboard Keyboard Figure 8-3: PS/2 Keyboard Scan Codes Tabl e 8 - 3 : Common PS/2 Keyboard Commands 76543210 Ignored Caps Num Mouse Mouse Arrow Vol ta ge Su pp ly Page Chapter 9 Digital to Analog Converter (DAC) SPI Communication Interface Signals Disable Other Devices on the SPI Bus to Avoid Contention SPI Communication Details Communication Protocol Specifying the DAC Output Voltage DAC Outputs A and B DAC Outputs C and D Page Chapter 10 Analog Capture Circuit Digital Outputs from Analog Inputs Programmable Pre-Amplifier Interface Programmable Gain SPI Control Interface Slave: LTC2624-1 Spartan-3E FPGA Master A Gain B Gain Analog to Digital Converter (ADC) Interface SPI Control Interface 80 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide Chapter 10: Analog Capture Circuit R Channel 1 The A/D converter sets its SDO output line to high impedance after 33 SPI_SCK clock cycles 32 SPI_SCK Disable Other Devices on the SPI Bus to Avoid Contention Connecting Analog Inputs Page Chapter 11 Intel StrataFlash Parallel NOR Flash PROM Spartan-3E FPGA Figure 11-1: Connections to Intel StrataFlash Flash Memory Intel StrataFlash CoolRunner-II CPLD StrataFlash Connections StrataFlash Connections Tabl e 1 1 - 1: FPGA-to-StrataFlash Connections Chapter 11: Intel StrataFlash Parallel NOR Flash PROM R Tabl e 1 1 - 1: FPGA-to-StrataFlash Connections Shared Connections Character LCD Xilinx XC2C64A CPLD SPI Data Line 88 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide Address Figure 11-3: UCF Location Constraints for StrataFlash Data I/Os Figure 11-2: UCF Location Constraints for StrataFlash Address Inputs Data Control Setting the FPGA Mode Select Pins Page Chapter 12 SPI Serial Flash Configuring from SPI Flash Setting the FPGA Mode Select Pins Creating an SPI Serial Flash PROM File Setting the Configuration Clock Rate Formatting an SPI Flash PROM File Page Page Page Downloading the Design to SPI Flash Downloading the SPI Flash using XSPI Download and Install the XSPI Programming Utility Attach a JTAG Parallel Programming Cable Insert Jumper on JP8 and Hold PROG_B Low Programming the SPI Flash with the XSPI Software GND JP8 GND JP8 Additional Design Details Shared SPI Bus with Peripherals Other SPI Flash Control Signals Variant Select Pins, VS[2:0] Jumper Block J11 Programming Header J12 Multi-Package Layout S Q W GND Page Chapter 13 DDR SDRAM Figure 13-1: FPGA Interface to Micron 512 Mbit DDR SDRAM All DDR SDRAM interface signals are terminated. MT46V32M16 (32Mx16) DDR SDRAM Connections DDR SDRAM Connections Tabl e 1 3 - 1: FPGA-to-DDR SDRAM Connections (Continued) Chapter 13: DDR SDRAM R Address Figure 13-3: UCF Location Constraints for DDR SDRAM Data I/Os Figure 13-2: UCF Location Constraints for DDR SDRAM Address Inputs Data Control Reserve FPGA VREF Pins Page Chapter 14 10/100 Ethernet Physical Layer Interface RJ-45 Ethernet Connector (J19) SMSC LAN83C185 10/100 Ethernet PHY Chapter 14: 10/100 Ethernet Physical Layer Interface R Ethernet PHY Connections RJ-45 MicroBlaze Ethernet IP Cores Page Chapter 15 Expansion Connectors Hirose 100-pin FX2 Edge Connector (J3) Voltage Supplies to the Connector Connector Pinout and FPGA Connections Hirose 100-pin Expansion Connector (J3) Spartan-3E FPGA Hirose 100-pin FX2 Edge Connector (J3) Tabl e 1 5 - 1: Hirose 100-pin FX2 Connector Pinout and FPGA Connections (J3) Compatible Board Mating Receptacle Connectors Differential I/O Hirose 100-pin FX2 Edge Connector (J3) Using Differential Inputs b) On-chip differential termination a) External 100W termination resistor Using Differential Outputs 122 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide Chapter 15: Expansion Connectors R Figure 15-7: UCF Location Constraints for Accessory Headers Six-Pin Accessory Headers Header J1 Header J2 Header J4 Connectorless Debugging Port Landing Pads (J6) Page Chapter 16 XC2C64A CoolRunner-II CPLD Chapter 16: XC2C64A CoolRunner-II CPLD R Figure 16-1: XC2C64A CoolRunner-II CPLD Controls Master Serial and BPI Configuration Modes UCF Location Constraints FPGA Connections to CPLD Figure 16-3: UCF Location Constraints for the XC2C64A CPLD Figure 16-2: UCF Location Constraints for FPGA Connections to CPLD CPLD Page Chapter 17 DS2432 1-Wire SHA-1 EEPROM Page Appendix A Schematics FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header Page RS-232 Ports, VGA Port, and PS/2 Port Page Page Page Voltage Regulators Page FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG Connections Page FPGA I/O Banks 0 and 1, Oscillators Page FPGA I/O Banks 2 and 3 Page Power Supply Decoupling Page XC2C64A CoolRunner-II CPLD Page Linear Technology ADC and DAC Page Page Page Buttons, Switches, Rotary Encoder, and Character LCD Page Page Page Page Appendix B Example User Constraints File (UCF)