80 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide

www.xilinx.com UG257 (v1.1) December 5, 2007
Chapter 10: Analog Capture Circuit RFigure 10-7 shows detailed transaction timing. The AD_CONV signal is not a traditional SPI slave select enable. Be sure to provide enough SPI_SCK clock cycles so that the ADC leaves the SPI_MISO signal in the high-impedance state. Otherwise, the ADC blocks communication to the other SPI peripherals. As shown in Figure10-6, use a 34-cyc le communications sequence. The ADC 3-states its data output for two clock cycles before and after each 14-bit data transfer.
UCF Location Constraints
Figure 10-8 provides the User Constraint File (UCF) constraints for the amplifier interface, including the I/O pin assignment and I/O standard used.Figure 10-6: Analog-to-Digital Conversion InterfaceFigure 10-7: Detailed SPI Timing to ADCSpartan-3EFPGA Master
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Converted data is presented with a latency of one sample.
The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV.
The converted values is then presented after the next AD_CONV pulse.
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Slave: LTC1407A-1 A/D Converter
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The A/D converter sets its SDO output line to high impedance after 33 SPI_SCK clock cycles
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