Acer TM7300 2.2.2 Architecture Block Diagram

2-6 Service Guide

The 82371AB PCI ISA IDE Xcelerator (PIIX4) is a multi-f unction PCI device implem enting a PCI-to-

ISA bridge func tion, a PCI IDE function, a Univers al Serial Bus host/hub func tion, and an Enhanc ed

Power Management f unction. As a PCI-to-ISA bridge, PIIX 4 integrates many com mon I/O f unctions

found in ISA-based PC systems—two 82C37 DMA Controllers, two 82C59 Interrupt Controllers, an

82C54 Timer/Counter, and a Real Time Clock. In addition to compatible transfers, each DMA

channel supports Type F transf ers. PIIX4 also contains full support for both PC/PCI and Distributed

DMA protocols im plementing PCI-based DMA. T he Interrupt Controller has Edge or Level sensitive

programmable inputs and fully supports the use of an external I/O Advanced Programmable

Interrupt Controller (APIC) and Serial Interrupts. Chip select decoding is provided for BIOS, Real

Time Clock, Keyboard Controller, second external microcontroller, as well as two Programmable

Chip Selects. PIIX4 provides full Plug and Play compatibility. PIIX4 can be configured as a

Subtractive Decode bridge or as a Positive Decode bridge. This allows the use of a subtractive

decode PCI-to-PCI bridge such as the Intel 380FB PCIset which implements a PCI/ISA docking

station environment.

PIIX4 supports two IDE connectors for up to four IDE devices providing an interface for IDE hard

disk s and CD ROMs. Up to four IDE devices can be s upported in Bus Master m ode. PIIX4 c ontains

support for “Ultra DMA/33” synchronous DMA compatible devices.

PIIX4 contains a Universal Serial Bus (USB) Host Controller that is Universal Host Controller

Interface (UHCI) compatible. The Host Controller’s root hub has two programmable USB ports.

PIIX4 supports Enhanced Power Management, including full Cloc k Control, Devic e Management f or

up to 14 devices, and Suspend and Resume logic with Power On Suspend, Suspend to RAM or

Suspend to Disk. It f ully supports Operating System Directed Power Managem ent via the Advanced

Configuration and Power Interface (ACPI) specification. PIIX4 integrates both a System

Management Bus (SMBus) Host and Slave interface for serial communication with other devices.

2.2.2 Architecture Block Diagram

The following is the architectural bloc k diagr am of the PIIX 4 with respec t to its implementation in this

notebook computer.

Figure 2-1 PIIX4 Architecture Block Diagram

Contents

Main Copyright Disclaimer Purpose Manual Structure Appendix D Schematics Appendix E BIOS POST Checkpoints Conventions Table of Contents Chapter 1 System Introduction Chapter 2 Major Chips Description Chapter 3 BIOS Setup Utility Chapter 4 Disassembly and Unit Replacement Page List of Figures Page List of Tables Page &KDSWHU&KDSWHU System Introduction Page System Introduction 1-3 1.2 Ports 1.2.1 Rear Panel Ports Figure 1-2 Rear Port Location Table 1-1 Rear Port Descriptions 1-4 Service Guide 1.2.2 Left Panel Ports Figure 1-3 Left Port Location System Introduction 1-5 Table 1-2 Left Port Descriptions 1.2.3 Indicator Lights Figure 1-4 Indicator Lights Table 1-3 Indicator Light Descriptions 1-6 Service Guide 1.2.4 Hot Keys Table 1-4 Hot Key Descriptions System Introduction 1-7 Table 1-4 Hot Key Descriptions Table 1-5 Eject Menu Item Descriptions 1-8 Service Guide 1.3 System Specification Overvi ew Table 1-6 System Specifications System Introduction 1-9 Table 1-6 System Specifications Page Page Page Page Page System Introduction 1-15 1.5 Jumpers and Connectors Figure 1-9 Mainboard Jumpers and Connectors (Top Side) 1.5.1 Mainboard 1-16 Service Guide Figure 1-10 Mainboard Jumpers and Connectors (Bottom Side) The following table shows the settings of the mainboards bottom side jumper pads. Table 1-7 Mainboard Jumpers Pads Settings (Bottom Side) 1.5.2 Media Board 1-18 Service Guide 1.6 System Configurations and Speci fi cations 1.6.1 System Memory Map Table 1-8 System Memory Map 1.6.2 Interrupt Channel Map Table 1-9 Interrupt Channel Map 1.6.4 DMA Channel Map Table 1-11 DMA Channel Map 1-20 Service Guide 1.6.5 GPIO Port Definition Map Table 1-12 GPIO Port Definition Map I System Introduction 1-21 Table 1-12 GPIO Port Definition Map I 1-22 Service Guide System Introduction 1-23 1.6.6 PCI Devices Assignment Table 1-14 PCI Devices Assignment 1-24 Service Guide 1.6.7 Power Management System Introduction 1-25 Table 1-15 PMU Timers List 1-26 Service Guide Table 1-15 PMU Timers List HDD power enable pinY15(PX3_HDPON). HDD reset [pinW14(PX3_HDRST#) of PIIX4]. CD-ROM buffer enable [pin-M3 of U21 PX3-FDDBEN of PIIX4]. CD-ROM power control [pin-T14 of U21(PX3_CD/FDPON) of PIIX4]. 1-28 Service Guide Modem power enable. System Introduction 1-29 Devices zero-clocked. Devices brought to a low power state. Devices turned off. System thermal alarm. 1-30 Service Guide Battery very low. Keystroke. Lid switch. Resume on schedule. 1.6.8 CPU Module Table 1-16 CPU Module Specifications System Introduction 1-31 1.6.9 BIOS Table 1-17 BIOS Specifications 1.6.10 System Memory Table 1-18 System Memory Specifications 1-32 Service Guide 1.6.11 Video Memory Table 1-20 Video Memory Specification System Introduction 1-33 1.6.12 Video Display Modes Table 1-21 Video Display Specification 1.6.12.1 External CRT Resolution Modes Table 1-22 External CRT Resolution Modes 1.6.12.2 LCD Resolution Modes 1.6.13 Audio Table 1-24 Audio Specifications 1.6.14 PCMCIA Table 1-25 PCMCIA Specifications System Introduction 1-35 1.6.15 Parallel Port Table 1-26 Parallel Port Specifications 1.6.16 Serial Port Table 1-27 Serial Port Specifications 1.6.17 Touchpad 1.6.18 SIR/FIR Table 1-29 SIR/FIR Specifications 1.6.19 LCD Table 1-30 LCD Specifications System Introduction 1-37 1.6.20 CD-ROM Table 1-31 CD-ROM Specifications 1.6.21 Diskette Drive Table 1-32 Diskette Drive Specifications 1-38 Service Guide 1.6.22 Hard Disk Drive Table 1-33 Hard Disk Drive Specifications 1.6.23 Keyboard Table 1-34 Keyboard Specifications System Introduction 1-39 1.6.24 Battery Table 1-35 Battery Specifications 1.6.25 DC-DC Converter Table 1-36 DC-DC Converter Specifications 1-40 Service Guide 1.6.26 DC-AC Inverter Table 1-37 DC-AC Inverter Specifications 1.6.27 AC Adapter Table 1-38 AC Adapter Specifications System Introduction 1-41 7100 System Block Diagram . . 32~128MB EDO/SDRAM memory . . 512KB L2 cache memory . 256KB PMU/System/Video BIOS . Intel 430TX Core Logic chipset . NS87338 Super I/O controlle r 970T SYSTEM BLOCK DIAGRAM System Introduction 1-43 1.8 Environmental Requirements Table 1-39 Environmental Requirements 1.9 Mechanical Specifications &KDSWHU&KDSWHU Major Chips Description Major Chips Description 2-1 This chapter discusses the major components. 2.1 Major Component List Table 2-1 Major Chips List 2.2 Intel PIIX4 Major Chips Description 2-3 2-4 Service Guide 2.2.1 Features Page 2-6 Service Guide 2.2.2 Architecture Block Diagram Figure 2-1 PIIX4 Architecture Block Diagram Page 2-8 Service Guide 2.2.4 Pin Descriptions Suspend/Resume and Power Plane Control Major Chips Description 2-9 2-10 Service Guide Major Chips Description 2-11 2-12 Service Guide Major Chips Description 2-13 2-14 Service Guide Table 2-2 82371AB Pin Descriptions Major Chips Description 2-15 PCI DMA 2-16 Service Guide Major Chips Description 2-17 Suspend/Resume and Resume Control Signaling 2-18 Service Guide Major Chips Description 2-19 2-20 Service Guide Major Chips Description 2-21 2-22 Service Guide Major Chips Description 2-23 2-24 Service Guide Major Chips Description 2-25 Table 2-2 82371AB Pin Descriptions 2-26 Service Guide Table 2-2 82371AB Pin Descriptions (continued) Name Type Description Major Chips Description 2-27 Table 2-2 82371AB Pin Descriptions (continued) 2-28 Service Guide 2.3 NM2160 2.3.1 Features Page Major Chips Description 2-31 2.3.3 Pin Descriptions Conventions used in the pin description types: 2-32 Service Guide Major Chips Description 2-33 2-34 Service Guide Major Chips Description 2-35 2-36 Service Guide Major Chips Description 2-37 Page Page Page Major Chips Description 2-41 2.4.4 Pin Descriptions Conventions used in the pin description types: Table 2-4 NMA1 Pin Descriptions 2-42 Service Guide Table 2-4 NMA1 Pin Descriptions Page Page Major Chips Description 2-45 2.5.3 Pin Diagram Figure 2-7 87C552 Pin Diagram 2-46 Service Guide 2.5.4 Pin Descriptions Table 2-5 87C552 Pin Descriptions Major Chips Description 2-47 Table 2-5 87C552 Pin Descriptions 2-48 Service Guide 2.6 NS97338VJG Super I/O Contr ol l er 2.6.1 Features Page 2-50 Service Guide 2.6.2 Block Diagram Figure 2-8 NS97338VJG Block Diagram Page 2-52 Service Guide 2.6.4 Pin Description Major Chips Description 2-53 Whenever the MSR DCTS bit is set, an interrupt is generated if Modem Status interrupts are enabled. Whenever the MSR DDCD bit is set, an interrupt is generated if Modem Status interrupts are enabled. 2-54 Service Guide Major Chips Description 2-55 2-56 Service Guide Major Chips Description 2-57 2-58 Service Guide Major Chips Description 2-59 2.7 CL-PD6832: PCI-to-CardBus Host Adapter 2.7.1 Features Page Major Chips Description 2-61 2-62 Service Guide The following table lists the pin descriptions LOCK# Major Chips Description 2-63 2-64 Service Guide Major Chips Description 2-65 2-66 Service Guide Major Chips Description 2-67 2-68 Service Guide Major Chips Description 2-69 2-70 Service Guide Major Chips Description 2-71 2-72 Service Guide 2.8 Ambit T62.036. C DC-DC Converter 2.8.1 Pin Diagram CN1 CN2 T62.036.C Major Chips Description 2-73 Table 2-8 T62.036.C Pin Descriptions 2-74 Service Guide 2.9 Ambit DC-AC Inverter CN1 T62.055.C 1 CN2 2.9.1 T62.055C 2.9.1.1 Pin Diagram 2.9.2 T62.088C 2.9.2.1 Pin Diagram Figure 2-13 T62.088.C Pin Diagram 2.9.2.2 Pin Descriptions Table 2-10 T62.088.C Pin Descriptions 2-76 Service Guide Table 2-10 T62.088.C Pin Descriptions &KDSWHU&KDSWHU BIOS Setup Information 3-2 Service Guide 3.1 About My Computer Table 1-1 About My Computer Parameters BIOS Setup Information 3-3 3.2 System Configuration 3.2.1 Date and Time 3.2.2 Floppy Drives 3.2.3 Hard Disks 3.2.4 Num Lock After Boot Page 3.3 Advanced System Configuration 3.3.1 Internal Cache 3.3.2 External Cache 3.3.3 Enhanced IDE Features 3.3.4 Onboard Communication Ports 3.3.5 Onboard USB 3.3.6 Reset PnP Resources 3.4 Power Saving Options 3.4.1 When Lid is Closed 3.4.2 Suspend to Disk on Critical Battery 3.4.3 Display Always On 3.4.5 Resume On Schedule 3.5 System Security 3.5.1 Supervisor and User Passwords 3-10 Service Guide 3.5.2 Diskette Drive Access Control Warning! Contact your dealer to upgrade your BIOS. 3.5.3 Hard Disk Drive Access Control 3.5.4 Start Up Sequences Table 1-2 Start Up Sequences Page &KDSWHU&KDSWHU Disassembly and Unit Replacement Page 4.1.2 Connector Types Page Page 4.2 Removing the Module 4.3 Replacing the Hard Disk Drive 4.4 Replacing Memory Page Page Page 4.6 Replacing the CPU Page Page Page Page Page Page 4.9 Disassembling the Display Page $S$SSHQGSHQGL[$L[$ Model Number Definition W: HDD & FDD & CD-ROM Model Number Definition A-1 This appendix shows the model number definition of the notebook. TravelMate 7300 VU - W X Y Z Z: Acer or TI logo Page Page Page Page $S$SSHQGSHQGL[&L[& Spare Parts List Spare Parts List C-1 This appendix lists the spare parts of the notebook computer. Table C-1 Spare Parts List C-2 Service Guide Table C-1 Spare Parts List $SSHQGL['$SSHQGL[' Schematics Schematics D-1 This appendix includes the schematic diagrams of the notebook. Table D-1 Schematics Diagram List Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page $SSHQGL[($SSHQGL[( BIOS POST Checkpoints BIOS POST Checkpoints E-1 This appendix lists the POST checkpoints of the notebook BIOS. E-2 Service Guide Note: The keyboard LEDs should flash once. BIOS POST Checkpoints E-3 Note: The FDD LED should flash once and its head should be positioned.