Major Chips Description 2-3

The tim er/counter block contains thr ee counters that are equivalent in func tion to those f ound in one
82C54 programmable interval timer. These three counters are combined to provide the system timer
function, refresh request, and speaker tone. The 14.31818-MHz oscillator input provides the clock
source for these three counters.
PIIX4 provides an ISA-Compatible interrupt controller that incorporates the functionality of two
82C59 interrupt controllers. The two interrupt controllers are cascaded so that 14 external and two
internal interrupts are possible. In addition, PIIX4 s upports a serial interr upt schem e. PIIX4 provides
full support for the use of an external IO APIC.
All of the regis ters in these m odules can be read and res tored. This is required to save and re store
system state after power has been removed and restored to the circuit.
Enhanced Universal Serial Bus (USB) Controller
The PIIX4 USB controller provides enhanced support for the Universal Host Controller Interface
(UHCI). This includes support that allows legacy software to use a USB-based keyboard and
mouse.
RTC
PIIX4 contains a Motorola* MC146818A-compatible real-tim e c lock with 256 bytes of battery-backed
RAM. The real-time clock performs two key functions: keeping track of the time of day and storing
system data, even when the system is powered down. The RTC operates on a 32.768-kHz crystal
and a separate 3V lithium battery that provides up to 7 years of protection.
The RT C also supports two lockable m em ory ranges. By setting bits in the c onfiguration s pace, two
8-byte ranges can be locked to read and write accesses. This prevents unauthorized reading of
passwords or other system security information.
The RTC also supports a date alarm, that allows for scheduling a wake up event up to 30 days in
advance, rather than just 24 hours in advance.
GPIO and Chip Selects
Various general purpos e inputs and outputs are provided f or custom system design. The num ber of
inputs and outputs varies depending on PIIX4 configuration. Two programmable chip selects are
provided which allows the designer to place devices on the X-Bus without the need for external
decode logic.
Pentium® and Pentium® II Processor Interface
The PIIX4 CPU interface allows connection to all Pentium and Pentium II processors. The Sleep
mode for the Pentium II processors is also supported.