Acer TM7300 2.2 Intel PIIX4

2.2 Intel PIIX4

PIIX4 is a multi-function PCI device that integrates many system-level functions.

PCI to ISA/EIO Bridge

PIIX4 is com patible with the PCI Rev 2.1 specific ation, as well as the IEEE 996 specific ation for the

ISA (AT) bus. On PCI, PIIX4 operates as a master for various internal modules, such as the USB

controller, DMA controller , IDE bus master c ontroller , dist ributed DMA master s , and on behalf of ISA

masters. PIIX4 operates as a slave for its internal registers or for cycles that are passed to the ISA

or EIO buses. All internal registers are positively decoded.

PIIX4 can be configured for a full ISA bus or a subset of the ISA bus called the Extended IO (EIO)

bus. The use of the EIO bus allows unused signals to be conf igured as general purpose inputs and

outputs. PIIX4 can directly drive up to five ISA slots without external data or address buffering. It

also provides byte-swap logic, I/O rec overy support, wait-state generation, and SYSCLK generation.

X-Bus chip selects are provided for Keyboard Controller, BIOS, Real Time Clock, a second

microcontroller, as well as two programmable chip selects.

PIIX4 can be configured as either a subtractive decode PCI to ISA bridge or as a positive decode

bridge. This gives a system designer the option of placing another subtractive decode bridge in the

system (e.g., an Intel 380FB Dock Set).

IDE Interface (Bus Master capability and synchronous DMA Mode)

The f ast IDE interf ace s upports up to f our IDE devices providing an interf ace f or IDE hard disk s and

CD ROMs.

Each IDE device can have independent tim ings . The IDE inter fac e supports PIO IDE transf ers up to

14 Mbytes/sec and Bus Master IDE transfers up to 33 Mbytes/sec. It does not consume any ISA

DMA resources. The IDE interface integrates 16x32-bit buffers for optimal transfers.

PIIX4’s IDE s ystem c ontains two independent IDE signal channels. T hey can be electric ally isolated

independently, allowing for the im plementation of a “glueless” Swap Bay. They can be configured to

the standard prim ary and secondary channels (f our devices) or prim ary drive 0 and prim ary drive 1

channels (two devices). This allows flexibility in system design and device power management.

Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)

The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven independently

programmable channels. Channels [0:3] are hardwired to 8-bit, count-by-byte transfers, and

channels [5:7] are hardwired to 16-bit, c ount-by-word transfers . Any two of the seven DMA channels

can be programmed to support fast Type-F transfers. The DMA controller also generates the ISA

refresh cycles.

The DMA controller supports two separate methods for handling legacy DMA via the PCI bus. The

PC/PCI protocol allows PCI-based peripherals to initiate DMA cycles by encoding requests and

grants via three PC/PCI REQ #/GNT# pairs . T he s ec ond method, Dist ributed DMA, allows r eads and

writes to 82C37 registers to be distributed to other PCI devices. The two methods can be enabled

concurrently. The serial interrupt scheme typically associated with Distributed DMA is also

supported.