Acnodes FPC 8084 DRAM Timing By SPD, DRAM Clock, SDRAM Cycle Length, Memory Hole, OnChip USB

FPC 8084 User’s Manual

DRAM Timing By SPD

This item is selected depending on whether the board has paged DRAMs or EDO (extended data output) DRAMs.

DRAM Clock

The DRAM clock value is set depending on whether the board has paged DRAMs or EDO (extended data output) DRAMs. The available choices are 66 MHz and Host CLK.

SDRAM Cycle Length

When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing. Do not reset this field from the default value specified by the system designer. The default setting is 3.

Memory Hole

To improve performance, certain space in memory is reserved for ISA cards. This memory must be mapped into the memory space below 16MB. The available choices are 15M-16M and Disabled.

P2C/C2P Concurrency

This item enables or disables the PCI to CPU and CPU to PCI concurrency. By default, this field is set to Enabled.

System BIOS Cacheable

Selecting “Enabled￿ allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in better system performance. However, if any program writes to this memory area, a system error may result.

The choice: Enabled, Disabled.

Video RAM Cacheable

Selecting “Enabled” allows caching of the A/B segment, resulting in better system performance.

The choice: Enabled, Disabled.

AGP Aperture Size

The field sets aperture size of the graphics. The aperture is a portion of the PCI memory address range dedicated for graphics memory address space. Host cycles that hit the aperture range are forwarded to the AGP without any translation.

The choice: 4M, 8M, 16M, 32M, 64M, 128M and 256M.

OnChip USB

This should be enabled if the system has a USB installed on the system board and the USB will be used. Even when equipped, if a higher performance controller is added, this feature should be disabled.

The choice: Enabled, Disabled.

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