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User’s Manual for Advantech SOM-A2558 series module V1.00
27
Sync input of the LCD panel. For
STN displays, this output connects
to the Frame Clock input of the
LCD panel.
This output indicates the start of a
new frame of pixels. The panel
needs to reset its line pointers to
the top of the screen.
198
GND P Ground -
199
M_DE O
Flat Panel Display Enable. This
signal is used as a data enable
when the pixel clock needs to latch
pixel data.
No pulling
200
SHCLK O
Flat Panel Pixel Clock. The active
edge of FPCLK is programmable.
The LCD panel uses this clock
when loading pixel data into its
Line Shift register. This signal
connects to the TXCLK input of the
LVDS transmitter.
No pulling
Pin
No.
Signals Type
Description Default
state
B1 nBUF_CS2 O
Static chip selects.
Chip selects to
static memory devices such as ROM
and Flash. Individually
programmable in the memory
configuration registers. This pin can
be used with variable latency I/O
devices. nBUF_CS2 directly connect
to SoC PXA255 nCS2. User
could
use this pin as chip select pin to
control the solution IC on carrier
board. This pin is reserved for user
to use.
Pull-high
with 100K
ohm
A1 ADDR15 O SoC PXA255 system address 15 No pulling
B2 ADDR14 O SoC PXA255 system address 14 No pulling
A2 ADDR13 O SoC PXA255 system address 13 No pulling
B3 ADDR12 O SoC PXA255 system address 12 No pulling
A3 ADDR11 O SoC PXA255 system address 11 No pulling
B4 ADDR10 O SoC PXA255 system address 10 No pulling
A4 ADDR9 O SoC PXA255 system address 9 No pulling
B5 ADDR8 O SoC PXA255 system address 8 No pulling
A5 ADDR24 O SoC PXA255 system address 24 No pulling
B6 ADDR25 O SoC PXA255 system address 25 No pulling
A6 nBUF_OE O Memory output enable pin.
Connect
No pulling