![](/images/new-backgrounds/1266639/26663963x1.webp)
Your ePlatform Partner
User’s Manual for Advantech
|
|
| to PXA255 GPIO82 (E16 pin). This |
| ||||||
|
|
| GPIO pin is available for user to use. |
| ||||||
|
|
| GPIO pin. The pin directly connects |
| ||||||
A45 | PXA_GP83 | IO | to PXA255 GPIO83 (E15 pin). This | No pulling | ||||||
|
|
| GPIO pin is available for user to use. |
| ||||||
|
|
| GPIO pin. The pin directly connects |
| ||||||
B46 | PXA_GP84 | IO | to PXA255 GPIO84 (D16 pin). This | No pulling | ||||||
|
|
| GPIO pin is available for user to use. |
| ||||||
|
|
| Static chip selects. Chip selects to |
| ||||||
|
|
| static memory devices such as ROM |
| ||||||
|
|
| and | Flash. |
| Individually |
| |||
|
|
| programmable | in | the | memory |
| |||
|
|
| configuration registers. nBUF_CS1 | Pull high | ||||||
A46 | nBUF_CS1 | O | can be used with variable latency I/O | with | ||||||
|
|
| devices. Advantech default uses this | 100Kohm | ||||||
|
|
| pin as storage flash chip select pin. If |
| ||||||
|
|
| no special | application, | Advantech |
| ||||
|
|
| strongly suggest user to open this |
| ||||||
|
|
| pin in CSB. |
|
|
|
|
|
| |
B47 | N.C. | - | N.C. just float this pin. |
|
| - | ||||
|
|
| Static chip selects. Chip selects to |
| ||||||
|
|
| static memory devices such as ROM |
| ||||||
|
|
| and Flash. Individually |
|
|
| ||||
|
|
| programmable | in | the | memory |
| |||
|
|
| configuration registers. nBUF_CS3 | Pull high | ||||||
|
|
| can be used with variable latency I/O | |||||||
A47 | nBUF_CS3 | O | with | |||||||
devices. |
|
|
|
|
| |||||
|
|
|
|
|
|
|
| 100Kohm | ||
|
|
| Advantech uses the pin as I/O | |||||||
|
|
| memory | block. | About | detail |
| |||
|
|
| description, |
| please | reference |
| |||
|
|
|
| Memory and |
| |||||
|
|
| Interrupt Map”. |
|
|
|
|
| ||
|
|
| Static chip selects. Chip selects to |
| ||||||
|
|
| static memory devices such as ROM |
| ||||||
|
|
| and | Flash. |
| Individually |
| |||
|
|
| programmable | in | the | memory |
| |||
|
|
| configuration registers. nBUF_CS5 |
| ||||||
|
|
| can be used with variable latency I/O | Pull high | ||||||
|
|
| devices. |
|
|
|
|
| ||
B48 | nBUF_CS5 | O |
|
|
|
|
| with | ||
Advantech default uses the pin as | ||||||||||
|
|
| 100Kohm | |||||||
|
|
| display chip | chip | select | pin. |
| |||
|
|
| nBUF_CS4 pin is used for SM501 on |
| ||||||
|
|
|
| |||||||
|
|
| no special | application, | Advantech |
| ||||
|
|
| strongly suggest user to open this |
| ||||||
|
|
| pin in CSB. |
|
|
|
|
|
| |
|
|
| Channel 1 DMA Request. Notifies |
| ||||||
A48 | DMA_REQ1 | I | the DMA Controller that an external | Pull low | ||||||
device requires a DMA transaction. If | with 1Kohm | |||||||||
|
|
| ||||||||
|
|
| user wants to design a controller in |
|
32