Advantech SOM-A2558 DATA16, DATA17, DATA18, DATA19, DATA20, DATA21, DATA22, DATA23, BUFDQM1

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User’s Manual for Advantech SOM-A2558 series module V1.00

A33	DATA16	IO	SoC PXA255 system data 16								No pulling
B34	DATA17	IO	SoC PXA255 system data 17								No pulling
A34	DATA18	IO	SoC PXA255 system data 18								No pulling
B35	DATA19	IO	SoC PXA255 system data 19								No pulling
A35	DATA20	IO	SoC PXA255 system data 20								No pulling
B36	DATA21	IO	SoC PXA255 system data 21								No pulling
A36	DATA22	IO	SoC PXA255 system data 22								No pulling
B37	DATA23	IO	SoC PXA255 system data 23								No pulling
	nBUF_SDCA		SDRAM	CAS.			Connect		to	the
A37		O	column address strobe (CAS) pins								No pulling
	S
			for all banks of SDRAM.
			SDRAM CS for banks 2. Connect to
B38	nBUF_SDCS	O	the chip select (CS) pins for SDRAM.								No pulling
	2		For the PXA255 processor nSDCS0
			can be Hi-Z, Nsdcs1-3 cannot.
			SDRAM DQM for data bytes 1.
A38	BUF_DQM1	O	Connect to the data output mask								No pulling
			enables (DQM) for SDRAM.
			SDRAM		Clock			2.	Connect
			BUF_SDCLK[2] to the clock pins of
			SDRAM in bank pairs 2/3. They are
			driven by either the internal memory
			controller clock, or the internal
			memory controller clock divided by
			2. At reset, all clock pins are free
	BUF_SDCLK		running	at	the		divide by		2	clock
B39		O	speed and may be turned off via free								No pulling
	2
			running control register bits in the
			memory	controller.				The	memory
			controller		also		provides		control
			register bits for clock division and
			deassertion of each SDCLK pin.
			SDCLK[2:1]				control		register
			assertion bits are always deasserted
			upon reset.
			IO Select 16. Acknowledge from the								Pull high
			PCMCIA		card		that	the	current
A39	nBUF_IOIS16	I									with
			address is a valid 16 bit wide I/O
											100Kohm
			address.
			PCMCIA		write		enable.		Performs
			writes to PCMCIA memory and to
B40	nBUF_PWE	O	PCMCIA attribute space. Also used								No pulling
			as the write enable signal for
			Variable Latency I/O.
			GPIO	pin.		Advantech			default
			function is used as matrix Keypad
A40	KEYPAD_IRQ	I	IRQ. The pin directly connects to								No pulling
			PXA255 GPIO2 (L13 pin). If user
			doesn’t	use		the matrix			key	pad

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