White Paper

7

PowerPC G5

Next-Generation PowerPC Architecture

The PowerPC G5 is fabricated using state-of- the-art 130-nanometer circuitry with more than 1130 feet of ultrathin wiring—nearly 800 times thinner than a human hair.

The PowerPC G5 is a highly parallel implementation of the PowerPC architecture, capable of handling multiple assorted tasks at the same time. It’s based on the execu- tion core of IBM’s 64-bit POWER4 processor—recipient of the Microprocessor Report’s 2001 Analyst’s Choice Award for Best Workstation/Server Processor, which recognizes excellence in semiconductor technology innovation, design, and implementation. With two double-precision floating-point units, advanced branch prediction logic, and a high-bandwidth frontside bus, the POWER4 drives IBM’s top-of-the-line pSeries 690 servers.

Apple collaborated with IBM to leverage this industry-leading design for the next generation of personal computing. The development of the PowerPC G5 builds on previous PowerPC designs, combining an optimized Velocity Engine with a superscalar, superpipelined execution core that supports up to 215 simultaneous in-flight instruc- tions. And all this power is fabricated in IBM’s state-of-the-art 130-nanometer process technology using high-performance silicon-on-insulator (SOI) transistors and copper interconnects.

Ultrafast Access to Data and Instructions

The PowerPC G5 features processing innovations that optimize the flow of data and instructions—making it ideal for media streaming, HD video editing, real-time effects, audio synthesis, image processing, 3D rendering, numerical analysis, and physical modeling.

It starts with 512K of L2 cache that provides the execution core with ultrafast access to data and instructions—up to 32 GBps. Instructions are prefetched from the L2 cache into a large, direct-mapped 64K L1 cache at up to 64 GBps. As they are accessed from the L1 cache, up to eight instructions are fetched per clock cycle. Next, instructions are decoded and divided into smaller, faster-executing operations. In addition, 32K of L1 data cache can prefetch up to eight active data streams simultaneously.

This efficient preparation maximizes processing speed as instructions are dispatched into the execution core and data is loaded into the registers.

Page 7
Image 7
Apple PowerPC G5 manual Next-Generation PowerPC Architecture, Ultrafast Access to Data and Instructions