Z87 Extreme4
DRAM Configuration
DRAM Tweaker
Fine tune the DRAM settings by leaving marks in checkboxes. Click OK to confirm and apply your new settings.
CAS# Latency (tCL)
The time between sending a column address to the memory and the beginning of the data in response.
RAS# to CAS# Delay (tRCD)
The number of clock cycles required between the opening of a row of memory and accessing columns within it.
Row Precharge Time (tRP)
The number of clock cycles required between the issuing of the precharge command and opening the next row.
RAS# Active Time (tRAS) |
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The number of clock cycles required between a bank active command and issuing the | ||
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precharge command. |
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75
