Asus P5PE-VM 2.4.2 Chipset, Configure DRAM Timing by SPD [Enabled], DRAM Burst Length [8 Clocks], DRAM CAS# Latency [2.5 Clocks], DRAM RAS# Precharge [4 Clocks]

2.4.2 Chi pset

The Chipset menu allows you to change the advanced chipset settings. Select an item then press <Enter> to display the sub-menu.

Advanced Chipset Settings

WARNING: Setting wrong values in below sections may cause the system to malfunction.

Configure DRAM Timing by SPD	[Enabled]
Performance Acceleration Mode	[Auto]
DRAM Idle Timer	[Auto]
DRAM Refresh Rate	[Auto]
Graphic Adapter Priority	[AGP/Int-VGA]
Graphics Aperture Size	[64MB]
MPS Revision	[1.4]

Confi gure DRAM Ti mi ng by SPD [Enabl ed]

When this item is enabled, the DRAM timing parameters are set according to the DRAM SPD (Serial Presence Detect). When disabled, you can manually set the DRAM timing parameters through the DRAM sub-items. The following sub-items appear when this item is Disabled.

Configuration options: [Disabled] [Enabled]

DRAM CAS# Latency [2.5 Clocks]

Controls the latency between the SDRAM read command and the time the data actually becomes available.

Configuration options: [2.0 Clocks] [2.5 Clocks] [3.0 Clocks]

DRAM RAS# Precharge [4 Clocks]

Controls the idle clocks after issuing a precharge command to the DDR SDRAM. Configuration options: [4 Clocks] [3 Clocks] [2 Clocks]

DRAM RAS# to CAS# Delay [4 Clocks]

Controls the latency between the DDR SDRAM active command and the read/write command. Configuration options: [4 Clocks] [3 Clocks] [2 Clocks]

DRAM Precharge Delay [8 Clocks]

Sets the RAS Activate timing to Precharge timing.

Configuration options: [8 Clock] [7 Clocks] [6 Clocks] [5 Clocks]

DRAM Burst Length [8 Clocks] Sets the DRAM Write Recover Time. Configuration options: [4 Clocks] [8 Clocks]

2-18 Chapter 2: BIOS setup