3 Chapter
Allows you to set the ratio between the CPU Core Clock and the BCLK Frequency. Use <+> and
[Enabled] | Enables the C1E support function. This item should be enabled in order to |
| enable the Enhanced Halt Sate. |
[Disabled] | Disables this function. |
[Enabled] | The processor fetches data and instructions from the memory into the |
| cache that are likely to be required in the near future. This reduces the |
| latency associated with memory reads. |
[Disabled] | Disables this function. |
[Enabled] | The processor fetches the currently requested cache line, as well as the |
| subsequent cache line. This reduces the cache latency by making the next |
| cache line immediately available if the processor requires it as well. |
[Disabled] | The processor fetches only the currently requested cache line. |
[Enabled] | Allows a hardware platform to run multiple operating systems separately |
| and simultaneously, enabling one system to virtually function as several |
| systems. |
[Disabled] | Disables this function. |
[Enabled] | Enables the overheated CPU to throttle its clock speed to cool down. |
[Disabled] | Disables this function. |
[Enabled] | Enables the |
[Disabled] | Forces the XD feature flag to always return to zero (0). |
The Intel
[Enabled] | Two threads per activated core are enabled. |
[Disabled] | Only one thread per activated core is enabled. |
Allows you to choose the number of CPU cores to activate in each processor package. Configuration options: [All] [1] [2]
A20M [Disabled][Enabled] | Allows Legacy OSes to be compatible with APs. |
[Disabled] | Disables this function. |
Chapter 3: BIOS setup |