Calibre UK PICA93LV Appendix a Parallel I2C Communications Adapter Status Codes, Bit 6 Not Used

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APPENDIX A Parallel I2C Communications Adapter Status Codes

This is an eight bit register, read using the getstatus routine. The bit definitions are as follows:

Bit 7 (MSB) - The Pending Interrupt Not (PIN) Bit

The PIN bit is a read-only flag which is used to synchronise serial communication. Each time a serial data transmission is initiated (by sendaddress routine or setting STA bit) the PIN will be set (= 1) automatically. After successful transmission of one byte (9 clock pulses, including acknowledge), this bit will be automatically reset (= 0) indicating a complete transmission. When the ENI bit (enable interrupt) is also set, the PIN triggers an external interrupt via the selected IRQ line when PIN is reset. When in receiver mode, the PIN is also reset on completion of each received byte. In polled applications, the PIN bit is tested (using the getstatus routine) to determine when a serial transmission has been completed. In receiver mode, the PIN bit is tested (using the readbyte function). When the PIN becomes set all other status bits will be reset, with the exception of the BB (not Bus Busy) bit.

In short, when transmitting data, if PIN = 0 then the data has been sent, if PIN = 1 then it has not. When receiving data, if PIN = 0 then there is unread received data ready to read, if PIN = 1 then either the data received has already been read, or no data has yet been received.

Bit 6 - Not Used

This bit is not currently used and will always = 0.

Bit 5 - The STS Bit

When in slave-receiver mode (i.e. transmission initiated by a master elsewhere on the I2C bus), the flag STS = 1 when an externally generated Stop condition is detected, otherwise STS = 0. This flag is used only in slave-receiver mode.

Bit 4 - The Bus Error (BER) Bit

BER = 1 when a misplaced Start or Stop has been detected, otherwise BER = 0. This can be quite serious since the I2C devices on the bus may be left in an undefined state after a bus error has occurred - in some circumstances the only way to get the bus going again may be to reset all the I2C devices on it.

Bit 3 - The Last Received Bit /Address 0 "General Call" Address Received (LRB/AD0) Bit

This dual function status bit holds the value of the last received bit over the I2C bus when AAS (Bit 2)

=0. Normally this will be the value of the slave acknowledge; thus checking for slave acknowledgement is done via testing of the LRB bit. When AAS (Bit 2) = 1 ("Addressed As Slave"), the Parallel I2C Communications Adapter has been addressed as a slave and the ADO bit will = 1 if the slave address received was the "General Call" address. For further information on the "General Call" Address, see the Philips data books referenced in Further Information Section of this User Manual.

Bit 2 - The Addressed As Slave (AAS) Bit

When acting as a slave-receiver, this flag is set = 1 when an incoming address over the I2C bus matches the value defined by the setup routine, or if the slave address received was the I2C bus "General Call" address (00 Hex). In all other circumstances, AAS = 0.

Bit 1 - The Lost Arbitration Bit (LAB)

This bit is set = 1 when, in multimaster operation (more than one master present on the I2C bus) arbitration is lost to another master on the I2C bus. In all other circumstances, LAB = 0.

Bit 0 - The Busy Bit (BB)

This is a read-only flag indicating when the I2C bus is in use. BB = 0 indicates that the bus is busy, and access is not possible (unless of course it is busy because the Parallel I2C Communications Adapter itself has control of the bus). This bit is set = 1 by Stop conditions and reset = 0 by Start conditions. In short, BB = 1 means that the bus is free and a new transmission can be started.

Issue 1.3 Page 28

22/07/99