Cypress CY25566 manual Application Schematic

CY25566

Application Schematic

In this example, the CY25566 is being driven by a 75-MHz reference clock.

S0 = 0 and S1 = 0 are programmed to select a BW of 2.5%. (Refer to Table 1 and 2.)

S2 = 0 and S3 = 1 are programmed to select the Group 2 range.

VDD = 3.30 VDC.

SSCLK1a = 75 MHz @ 2.5% center spread modulation. SSCLK1b = 75 MHz @ 2.5% center spread modulation. SSCLK 2 = 37.5 MHz @ 2.5% center spread modulation. REFOUT = 37.5 MHz non-modulated clock.

VDD
0.1 uF
75 MHz Clock source 1		4
	XIN/CLKIN	VDD
				3
			REFOUT		REFOUT
16	XOUT
			SSCLK2	15	SSCLK2
2	CY25566
	REFOFF			8
VDD
			SSCLK1a		SSCLK1a
10	SSCC
7	S3
6				9
	S2		SSCLK1b		SSCLK1b
12
	S1
13	S0 VSS	VSS	VSS
	5	11	14

Figure 4. Application Schematic

Document #: 38-07429 Rev. *B Page 6 of 9

[+] Feedback