Cypress CY62136VN Switching Waveforms

CY62136VN MoBL®

Document #: 001-06510 Rev. *A Page 7 of 12

Write Cycle No. 1 (WE Controlled)[12, 17, 18]

Write Cycle No. 2 (CE Controlled)[12, 17, 18]

Notes:

17.Data I/O is high impedance if OE = VIH.

18.If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

19.During this period, the I/Os are in output state and input signals should not be applied.

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tWC

DATA I/O

ADDRESS

tHZOE

DATA

INVALID

NOTE19

BHE/BLE tBW

tWC

tAW

tSA

tHA

tHD

tSD

tSCE

DATA

INVALID

tBW

tPWE

ADDRESS

BHE/BLE

DATA I/O

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Contents

Main 2-Mbit (128K x 16) Static RAM CY62136VN MoBL Features Functional Description Logic Block Diagram CY62136VN MoBL Document #: 001-06510 Rev. *A Page 2 of 12 Product Portfolio Product VCC Range (V) Speed Ranges CY62136VN MoBL Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform Switching Characteristics CY62136VN MoBL Document #: 001-06510 Rev. *A Page 6 of 12 Switching Waveforms Read Cycle No. 1 Read Cycle No. 2 Switching Waveforms Write Cycle No. 3 (WE Controlled, OE LOW)[13, 18] Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[19] Switching Waveforms NOTE 19 Typical DC and AC Characteristics Truth Table Ordering Information Package Diagrams Package Diagrams 51-85096-*F 1.20MAX. 48-Ball (7.00 mm x 7.00 mm) FBGA (51-85096) Document History Page