Cypress CY62157ESL Switching Waveforms

CY62157ESL MoBL®

Document #: 001-43141 Rev. ** Page 8 of 12

Figure 4. Write Cycle No 1: WE Controlled [13, 17, 18]

Figure 5. Write Cycle 2: CE Controlled [13, 17, 18]

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tWC

tHZOE

DATAIN

NOTE 19

tBW

tSCE

DATA IO

ADDRESS

BHE/BLE

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

DATAIN

tBW

tSA

ADDRESS

DATA IO

BHE/BLE

NOTE 19

Notes

17.Data IO is high impedance if OE = VIH.

18.If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.

19.During this period, the IOs are in output state. Do not apply input signals.

[+] Feedback [+] Feedback

Contents

Main CY62157ESL MoBL 8-Mbit (512K x 16) Static RAM Features Functional Description Logic Block Diagram CY62157ESL MoBL Document #: 001-43141 Rev. ** Page 2 of 12 Pin Configuration Figure 1. 44-Pin TSOP II (Top View) Product Portfolio Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms CY62157ESL MoBL Data Retention Characteristics Data Retention Waveform CY62157ESL MoBL Switching Characteristics CY62157ESL MoBL Switching Waveforms Figure 2. Read Cycle No.1: Address Transition Controlled. [14, 15] Figure 3. Read Cycle No. 2: OE Controlled [15, 16] Figure 4. Write Cycle No 1: WE Controlled [13, 17, 18] Switching Waveforms Figure 6. Write Cycle 3: WE controlled, OE LOW [18] Figure 7. Write Cycle 4: BHE/BLE Controlled, OE LOW [18] Switching Waveforms Truth Table Ordering Information Page Document History Page