128K x 8 Static RAM

CY7C1019BN

CypressSemiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-06425 Rev. ** Revised February 1, 2006

Features

•High speed
—t
AA = 12, 15 ns
• CMOS for optimum speed/power
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Functionally equivalent to CY7C1019

Functional Description

The CY7C1019BN is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019BN is available in standard 32-pin TSOP Type
II and 400-mil-wide SOJ packages.
14
15

Logic Block Diagram Pin Configurations

A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUTBUFFER
POWER
DOWN
WE
OE
I/O0
I/O1
I/O2
I/O3
512x 256 x 8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
A11
A13
A12
A
A10
CE
A
A16
A9
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
Top Vi ew
SOJ
12
13
29
32
31
30
16
15 17
18
A7
A1
A2
A3
CE
I/O0
I/O1
VCC
A13
A16
A15
OE
I/O7
I/O6
A12
A11
A10
A9
I/O2
A0
A4
A5
A6
I/O4
VCC
I/O5
A8
I/O3
WE
VSS
A14
VSS
/ TSOPII
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