
CY7C1019BN
AC Test Loads and Waveforms
R1 480Ω |
5V |
OUTPUT |
30 pF
INCLUDING
JIG AND
SCOPE (a)
5V | R1 480Ω |
3.0V | |
OUTPUT |
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R2 | 5 pF |
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| R2 | GND |
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255Ω |
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| 255Ω | ≤ 3 ns | |
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| INCLUDING |
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| JIG AND | (b) |
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| SCOPE |
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ALL INPUT PULSES
90%
10%
90%
10%
≤ 3 ns
Equivalent to: THÉVENIN EQUIVALENT |
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OUTPUT | 167Ω | 1.73V | |||
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Switching Characteristics[4] Over the Operating Range
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Parameter |
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| Description |
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| Unit | |
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| Min. |
| Max. | Min. |
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Read Cycle |
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tRC |
| Read Cycle Time | 12 |
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| 15 |
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tAA |
| Address to Data Valid |
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| 12 |
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| 15 | ns | |||
tOHA |
| Data Hold from Address Change | 3 |
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| 3 |
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tACE |
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| LOW to Data Valid |
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| 12 |
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| 15 | ns | |
CE |
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tDOE |
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| LOW to Data Valid |
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| 7 | ns | |
OE |
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tLZOE |
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| LOW to Low Z | 0 |
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| 0 |
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OE |
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tHZOE |
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| HIGH to High Z[5, 6] |
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| 7 | ns | |
OE |
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tLZCE |
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| LOW to Low Z[6] | 3 |
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CE |
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t |
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| HIGH to High Z[5, 6] |
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| 7 | ns |
CE |
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HZCE |
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tPU |
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| LOW to | 0 |
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| 0 |
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CE |
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tPD |
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| HIGH to |
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| 15 | ns | ||
CE |
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Write Cycle[7, 8] |
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tWC |
| Write Cycle Time | 12 |
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| 15 |
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tSCE |
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| LOW to Write End | 9 |
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| 10 |
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CE |
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tAW |
| Address | 8 |
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| 10 |
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tHA |
| Address Hold from Write End | 0 |
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| 0 |
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tSA |
| Address | 0 |
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| 0 |
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tPWE |
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| Pulse Width | 8 |
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| 10 |
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WE |
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tSD |
| Data | 6 |
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| 8 |
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tHD |
| Data Hold from Write End | 0 |
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| 0 |
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t |
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| HIGH to Low Z[6] | 3 |
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WE |
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LZWE |
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t |
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| LOW to High Z[5, 6] |
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WE |
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HZWE |
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Notes:
4.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and
5.tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from
6.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7.The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data
8.The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: | Page 3 of 8 |
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