Cypress CY7C1019CV33 AC Test Loads and Waveforms4, Parameter Description Unit Min Max Read Cycle

CY7C1019CV33

AC Test Loads and Waveforms[4]

R 317Ω

3.3V

OUTPUT

30 pF	R2
	351Ω

(a)

3.0V

GND

Rise Time: 1 V/ns

ALL INPUT PULSES	High-Z characteristics:
	R 317	Ω

90%	90%	3.3V
10%	10%	OUTPUT
		5 pF

(b) Fall Time: 1 V/ns

(c)

R2

351Ω

Switching Characteristics Over the Operating Range[5]

			-10			-12			-15
Parameter		Description									Unit
			Min.	Max.	Min.		Max.	Min.		Max.
Read Cycle
tRC	Read Cycle Time		10		12			15			ns
tAA	Address to Data Valid			10			12			15	ns
tOHA	Data Hold from Address Change		3		3			3			ns
tACE		LOW to Data Valid		10			12			15	ns
	CE
tDOE		LOW to Data Valid		5			6			7	ns
	OE
tLZOE		LOW to Low Z	0		0			0			ns
	OE
tHZOE		HIGH to High Z[6, 7]		5			6			7	ns
	OE
tLZCE		LOW to Low Z[7]	3		3			3			ns
	CE
tHZCE	CE	HIGH to High Z[6, 7]		5			6			7	ns
tPU[8]		LOW to Power-Up	0		0			0			ns
	CE
tPD[8]		HIGH to Power-Down		10			12			15	ns
	CE
Write Cycle[9, 10]
tWC	Write Cycle Time		10		12			15			ns
tSCE	CE	LOW to Write End	8		9			10			ns
tAW	Address Set-Up to Write End		8		9			10			ns
tHA	Address Hold from Write End		0		0			0			ns
tSA	Address Set-Up to Write Start		0		0			0			ns
tPWE		Pulse Width	7		8			10			ns
	WE
tSD	Data Set-Up to Write End		5		6			8			ns
tHD	Data Hold from Write End		0		0			0			ns
tLZWE		HIGH to Low Z[7]	3		3			3			ns
	WE
tHZWE		LOW to High Z[6, 7]		5			6			7	ns
	WE

Notes:

4.AC characteristics (except High-Z) for all speeds are tested using the Thevenin load shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c).

5.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.

6.tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.

7.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

8.This parameter is guaranteed by design and is not tested.

9.The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.

10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

Document #: 38-05130 Rev. *F Page 4 of 10

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