Cypress CY7C1019CV33 manual Package Diagrams continued, pin TSOP II, + Feedback

Models: CY7C1019CV33

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CY7C1019CV33

51-85095-**

Document #: 38-05130 Rev. *F

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Contents

Features Logic Block DiagramPin Configuration CMOS for optimum speed/power Data retention atPin Configuration1 Selection Guide 48-ball VFBGA Top ViewUnit CY7C1019CV33Electrical Characteristics Over the Operating Range Maximum RatingsOperating Range Capacitance3Switching Characteristics Over the Operating Range5 AC Test Loads and Waveforms4Read Cycle Write Cycle 9Switching Waveforms Read Cycle No. 111Read Cycle No. 2 OE Controlled 12 Write Cycle No. 1 CE Controlled14Switching Waveforms continued PowerTruth Table Write Cycle No. 2 WE Controlled, OE HIGH During Write14Package Diagrams DiagramOrdering Information SpeedPackage Diagrams continued 32-pin TSOP IICY7C1019CV33 + Feedback48-ball VFBGA 6 x 8 x 1 mm Package Diagrams continuedCY7C1019CV33 Page 9 ofIssue Document History PageDocument Title CY7C1019CV33 128K x 8 Static RAM Document Number ECN NO