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Cypress CY7C1166V18, CY7C1168V18, CY7C1170V18, CY7C1177V18 Switching Waveform

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CY7C1166V18, CY7C1177V18

CY7C1168V18, CY7C1170V18

Document Number: 001-06620 Rev. *D Page 23 of 27

Switching Waveform

Read/Write/Deselect Sequence

Figure 7. Waveform for 2.5 Cycle Read Latency[28, 29]

12345678910

READ READ

NOP WRITEWRITE

NOP

11

R/W

tKH tKL tCYC

tHC

tSA tHA

DON’T CARE UNDEFINED

A0 A1 A2 A3 A4

QVLD

NOP

tCCQO

tCQOH

tCCQO

tCQOH

QVLD

KHKH

READ

(Read Latency = 2.5 Cycles)

NOP NOP

tCLZ tCHZ

CQDOH

Q00 Q11

Q01 Q10

tDOH

tCO

Q40

tSD

tHD

D20 D21 D30 D31

tCQD

tCQH tCQHCQH

Notes

28.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1.

29.Outputs are disabled (High-Z) one clock cycle after a NOP.

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Contents

Main CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Functional Description Selection Guide Logic Block Diagram (CY7C1166V18) Logic Block Diagram (CY7C1177V18) 1M x 8 Array 1M x 8 Array 1M x 9 Array 1M x 9 Array Logic Block Diagram (CY7C1168V18) Logic Block Diagram (CY7C1170V18) 512K x 18 Array 512K x 18 Array 256K x 36 Array 256K x 36 Array Pin Configurations CY7C1166V18 (2M x 8) 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1177V18 (2M x 9) Pin Configurations CY7C1168V18 (1M x 18) 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1170V18 (512K x 36) CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Pin Definitions CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Pin Definitions CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Functional Overview Read Operations Write Operations Byte Write Operations Truth Table BUS MASTER (CPU or ASIC) SRAM#1 SRAM#2 Write Cycle Descriptions CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select Test Data-In (TDI) Page TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical Characteristics CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 TAP AC Switching Characteristics TAP Timing and Test Condition CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Boundary Scan Order Power Up Sequence in DDR-II+ SRAM Power Up Sequence DLL Constraints Power Up Waveforms K K Maximum Ratings Operating Range Electrical Characteristic AC Input Requirements Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveform Read/Write/Deselect Sequence [+] Feedback [+] Feedback READ READ 12345678910 Page Ordering Information Package Diagram Figure 8. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 [+] Feedback [+] Feedback SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40 MAX. Document History Page