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Cypress CY7C1170V18, CY7C1168V18 manual Switching Waveform, Read/Write/Deselect Sequence, Nop

Models: CY7C1166V18 CY7C1177V18 CY7C1170V18 CY7C1168V18

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CY7C1166V18, CY7C1177V18

CY7C1168V18, CY7C1170V18

Switching Waveform

Read/Write/Deselect Sequence

Figure 7. Waveform for 2.5 Cycle Read Latency[28, 29]

NOP

tKH

	READ	READ	NOP	NOP	NOP	WRITE	WRITE	READ	NOP	NOP
	2	3	4	5	6	7	8	9	10	11	12
tKL	tCYC	tKHKH

K
LD
t	t
R/W

A0	A1			A2	A3	A4
	t						tQVLD
tSA tHA	tQVLD						tQVLD
QVLD				tHD		tHD
				tHD	tSD	tHD
				tSD	tSD
DQ	Q00 Q01	Q10		Q11	D20 D21	D30 D31	Q40
DQ		tDOH
	tCLZ	tDOH		tCHZ
	tCO			tCQD
(Read Latency = 2.5 Cycles)				tCQDOH
	tCCQO			tCQDOH
	tCQOH
CQ		t			tCQH	tCQHCQH
	tCQOH	t	CCQO		tCQH	tCQHCQH
			CCQO

CQ
						DON’T CARE	UNDEFINED

Notes

28.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1.

29.Outputs are disabled (High-Z) one clock cycle after a NOP.

Document Number: 001-06620 Rev. *D

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Cypress CY7C1170V18, CY7C1168V18, CY7C1166V18, CY7C1177V18 manual Switching Waveform, Read/Write/Deselect Sequence, Nop

Contents

Description 400 MHz 375 MHz 333 MHz 300 MHz Unit FeaturesConfigurations Selection Guide Functional Description Logic Block Diagram CY7C1177V18 Logic Block Diagram CY7C1166V18 Logic Block Diagram CY7C1170V18 Logic Block Diagram CY7C1168V18 TMS Pin ConfigurationsCY7C1166V18 2M x CY7C1177V18 2M x TMS TDI CY7C1168V18 1M xCY7C1170V18 512K x BWS Negative Input Clock Input Pin DefinitionsPin Name Pin Description Synchronous Read/Write Input. When TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for Jtag Functional Overview Operation Truth TableSRAM#1 SRAM#2 Master During the Data portion of a write sequence Write Cycle DescriptionsComments Remains unaltered Device. D80 and D3518 remains unaltered Write cycle descriptions of CY7C1170V18 followsDevice Into the device. D359 remains unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode Shows the tap controller state diagram TAP Controller State Diagram Parameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics TAP Controller TAP Timing and Test Condition TAP AC Switching Characteristics Instruction Codes Identification Register DefinitionsScan Register Sizes Bit # Bump ID Boundary Scan Order DLL Constraints Power Up Sequence in DDR-II+ SramPower Up Sequence Power Up Waveforms AC Input Requirements Electrical CharacteristicMaximum Ratings Operating Range Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance AC Test Loads and Waveforms DLL Timing Parameter Min MaxHigh LOW NOP Switching WaveformRead/Write/Deselect Sequence Ordering Information 333 Ball Fbga 13 x 15 x 1.4 mm Package Diagram VKN/KKVTMP ECN No Issue Date Orig. Description of ChangeDocument History NXR

Switching Waveform

Read/Write/Deselect Sequence

Figure 7. Waveform for 2.5 Cycle Read Latency[28, 29]

NOP

READ

NOP

WRITE

tKHKH

QVLD

CCQO