Cypress CY7C1166V18, CY7C1168V18, CY7C1170V18, CY7C1177V18 - page 24

CY7C1166V18, CY7C1177V18

CY7C1168V18, CY7C1170V18

Document Number: 001-06620 Rev. *D Page 24 of 27

Ordering Information

Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com

for actual products offered.

Speed

(MHz) Ordering Code Package

Diagram Package Type Operating

Range

400 CY7C1166V18-400BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1177V18-400BZC

CY7C1168V18-400BZC

CY7C1170V18-400BZC

CY7C1166V18-400BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1177V18-400BZXC

CY7C1168V18-400BZXC

CY7C1170V18-400BZXC

CY7C1166V18-400BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial

CY7C1177V18-400BZI

CY7C1168V18-400BZI

CY7C1170V18-400BZI

CY7C1166V18-400BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1177V18-400BZXI

CY7C1168V18-400BZXI

CY7C1170V18-400BZXI

375 CY7C1166V18-375BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1177V18-375BZC

CY7C1168V18-375BZC

CY7C1170V18-375BZC

CY7C1166V18-375BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1177V18-375BZXC

CY7C1168V18-375BZXC

CY7C1170V18-375BZXC

CY7C1166V18-375BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial

CY7C1177V18-375BZI

CY7C1168V18-375BZI

CY7C1170V18-375BZI

CY7C1166V18-375BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1177V18-375BZXI

CY7C1168V18-375BZXI

CY7C1170V18-375BZXI

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Contents

Main CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Functional Description Selection Guide Logic Block Diagram (CY7C1166V18) Logic Block Diagram (CY7C1177V18) 1M x 8 Array 1M x 8 Array 1M x 9 Array 1M x 9 Array Logic Block Diagram (CY7C1168V18) Logic Block Diagram (CY7C1170V18) 512K x 18 Array 512K x 18 Array 256K x 36 Array 256K x 36 Array Pin Configurations CY7C1166V18 (2M x 8) 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1177V18 (2M x 9) Pin Configurations CY7C1168V18 (1M x 18) 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1170V18 (512K x 36) CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Pin Definitions CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Pin Definitions CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Functional Overview Read Operations Write Operations Byte Write Operations Truth Table BUS MASTER (CPU or ASIC) SRAM#1 SRAM#2 Write Cycle Descriptions CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select Test Data-In (TDI) Page TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical Characteristics CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 TAP AC Switching Characteristics TAP Timing and Test Condition CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Boundary Scan Order Power Up Sequence in DDR-II+ SRAM Power Up Sequence DLL Constraints Power Up Waveforms K K Maximum Ratings Operating Range Electrical Characteristic AC Input Requirements Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveform Read/Write/Deselect Sequence [+] Feedback [+] Feedback READ READ 12345678910 Page Ordering Information Package Diagram Figure 8. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 [+] Feedback [+] Feedback SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40 MAX. Document History Page