Switching Waveforms, Read Cycle Timing17

CY7C1346H

Switching Waveforms

tCYC

CLK

tCH

tADS tADH

tAS tAH

tCL

tADS tADH

ADDRESS

GW, BWE,

BW[A:D]

tCES tCEH

Note:

17. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05672 Rev. *B

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Contents

Cypress Semiconductor Corporation FeaturesLogic Block Diagram 166 MHz Unit Pin ConfigurationSelection Guide CY7C1346H Byte Write Select Inputs, active LOW . Qualified with Power supply inputs to the core of the devicePin Definitions Name Description Functional Overview Burst Sequences Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND ZZ Mode Electrical Characteristics Adsp Adsc ADV Write CLK Next Cycle Add. Used Function Truth Table for Read/Write2 Ambient Range Maximum RatingsOperating Range AC Test Loads and Waveforms Capacitance10Thermal Resistance10 Switching Characteristics Over the Operating Range 11 Read Cycle Timing17 Switching Waveforms ADV Write Cycle Timing17 CLZ Read/Write Cycle Timing17, 19 DON’T Care ZZ Mode Timing 21 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsOrdering Information RXU Issue Date Orig. Description of ChangeDocument History PCI