Read/Write Cycle Timing17, 19, Clz | Cypress CY7C1346H specs

CY7C1346H

Read/Write Cycle Timing[17, 19, 20]

A3 A4

tWES tWEH

tDS tDH

A5 A6

D(A3)

tOELZ

Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)

D(A5) D(A6)

Back-to-Back READs

Single WRITE	BURST READ
DON’T CARE	UNDEFINED

Back-to-Back

WRITEs

Notes:

19.The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.

20.GW is HIGH.

Document #: 38-05672 Rev. *B

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Contents

Logic Block Diagram FeaturesCypress Semiconductor Corporation Selection Guide Pin ConfigurationCY7C1346H 166 MHz Unit Pin Definitions Power supply inputs to the core of the deviceName Description Byte Write Select Inputs, active LOW . Qualified with Functional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Burst Sequences Adsp Adsc ADV Write CLK Next Cycle Add. Used Function Truth Table for Read/Write2 Operating Range Maximum RatingsAmbient Range Thermal Resistance10 Capacitance10AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 11 Read Cycle Timing17 Switching Waveforms ADV Write Cycle Timing17 CLZ Read/Write Cycle Timing17, 19 DON’T Care ZZ Mode Timing 21 Ordering Information Package DiagramsPin Tqfp 14 x 20 x 1.4 mm Document History Issue Date Orig. Description of ChangePCI RXU