Cypress CY7C1346H manual Switching Waveforms continued, Write Cycle Timing17, + Feedback

Models: CY7C1346H

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CY7C1346H

CLK

ADSP

ADSC

ADDRESS

BWE,

BW[A :D]

ADV

Data In (D)

tWES tWEH

Data Out (Q)

BURST READ	Single WRITE	BURST WRITE
	DON’T CARE	UNDEFINED

Note:

18. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.

Extended BURST WRITE

Document #: 38-05672 Rev. *B

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Contents

Features Logic Block DiagramCY7C1346H Functional DescriptionPin Configuration Selection GuideCY7C1346H 100-pin TQFP PinoutPin Definitions CY7C1346HPin Definitions continued Functional OverviewCY7C1346H ZZ Mode Electrical Characteristics Burst SequencesInterleaved Burst Address Table MODE = Floating or VDD Linear Burst Address Table MODE = GNDCY7C1346H Truth Table 2, 3, 4, 5Truth Table for Read/Write2 CY7C1346HTruth Table continued2, 3, 4, 5, 6 Maximum Ratings Operating RangeElectrical Characteristics Over the Operating Range 8 CY7C1346HCapacitance10 Thermal Resistance10AC Test Loads and Waveforms CY7C1346HSwitching Characteristics Over the Operating Range 11 CY7C1346HSwitching Waveforms CY7C1346HRead Cycle Timing17 + FeedbackSwitching Waveforms continued CY7C1346HWrite Cycle Timing17 + FeedbackSwitching Waveforms continued CY7C1346HRead/Write Cycle Timing17, 19 Page 13 ofSwitching Waveforms continued CY7C1346HZZ Mode Timing 21 Page 14 ofPackage Diagrams Ordering InformationCY7C1346H CommercialDocument History Page Issue DateCY7C1346H Document Title CY7C1346H 2-Mbit 64K x 36 Pipelined Sync SRAM