Cypress CY7C1350G manual Functional Overview

		CY7C1350G
Pin Definitions (continued)
Name	I/O	Description
ZZ	Input-	ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
	Asynchronous	with data integrity preserved.During normal operation, this pin has to be low or left floating. ZZ pin
		has an internal pull-down.
DQs	I/O-	Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered
	Synchronous	by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
		specified by the address during the clock rise of the read cycle. The direction of the pins is
		controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as
		outputs. When HIGH, DQs and DQPX are placed in a tri-state condition. The outputs are automati-
		cally tri-stated during the data portion of a write sequence, during the first clock when emerging from
		a deselected state, and when the device is deselected, regardless of the state of OE.
DQP[A:D]	I/O-	Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
	Synchronous	sequences, DQP[A:D] is controlled by BW[A:D] correspondingly.
MODE	Input	Mode Input. Selects the burst order of the device. When tied to GND selects linear burst
	Strap pin	sequence. When tied to VDD or left floating selects interleaved burst sequence.
VDD	Power Supply	Power supply inputs to the core of the device.
VDDQ	I/O Power Supply	Power supply for the I/O circuitry.
VSS	Ground	Ground for the device.
NC		No Connects. Not internally connected to the die. 9M, 18M, 36M, 72M, 144M and 288M are
		address expansion pins in this device and will be used as address pins in their respective densities.

Functional Overview

The CY7C1350G is a synchronous-pipelined Burst SRAM designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250-MHz device).

Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BW[A:D] can be used to conduct Byte Write operations.

Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation.

Single Read Accesses

A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core

and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus, provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will tri-state following the next clock rise.

Burst Read Accesses

The CY7C1350G has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the Write signal WE is asserted LOW. The address presented to the address inputs is loaded into the Address Register. The write signals are latched into the Control Logic block.

Document #: 38-05524 Rev. *F Page 4 of 15

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