Cypress CY7C1350G manual Maximum Ratings, Operating Range, Power Applied

CY7C1350G

Maximum Ratings

(Above which the useful life may be impaired. For user guide- lines, not tested.)

Storage Temperature		−65°C to +150°C
Ambient Temperature with
Power Applied		−55°C to +125°C
Supply Voltage on VDD Relative to GND		−0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND		−0.5V to +VDD
DC Voltage Applied to Outputs
in tri-state	−0.5V to VDDQ + 0.5V

DC Input Voltage		−0.5V to VDD + 0.5V
Current into Outputs (LOW)			20 mA
Static Discharge Voltage			> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current			> 200 mA
Operating Range
	Ambient
Range	Temperature (TA)	VDD	VDDQ
Commercial	0°C to +70°C	3.3V – 5%	2.5V – 5%
		+10%	to VDD
Industrial	−
	40°C to +85°C

Electrical Characteristics Over the Operating Range[10, 11]

Parameter		Description			Test Conditions		Min.		Max.		Unit
VDD		Power Supply Voltage					3.135		3.6		V
VDDQ		I/O Supply Voltage					2.375		VDD		V
VOH		Output HIGH Voltage	for 3.3V I/O, IOH = −4.0 mA				2.4				V
			for 2.5V I/O, IOH = −1.0 mA				2.0				V
VOL		Output LOW Voltage	for 3.3V I/O, IOL= 8.0 mA						0.4		V
			for 2.5V I/O, IOL=1.0 mA						0.4		V
V	IH	Input HIGH Voltage[10]	V	DDQ	= 3.3V		2.0	V	DD	+ 0.3V	V
			VDDQ = 2.5V				1.7	VDD + 0.3V			V
VIL		Input LOW Voltage[10]	VDDQ = 3.3V				–0.3		0.8		V
			VDDQ = 2.5V				–0.3		0.7		V
IX		Input Leakage Current	GND ≤ VI ≤ VDDQ				−5			5	∝A
		except ZZ and MODE
		Input Current of MODE	Input = VSS				−30				∝A
			Input = VDD							5	∝A
		Input Current of ZZ	Input = VSS				–5				∝A
			Input = VDD						30		∝A
IOZ		Output Leakage	GND ≤ VI ≤ VDDQ, Output Disabled				−5			5	∝A
		Current
IDD		VDD Operating Supply	VDD = Max., IOUT = 0 mA,			4-ns cycle, 250 MHz			325		mA
		Current	f = fMAX = 1/tCYC
						5-ns cycle, 200 MHz			265		mA
						6-ns cycle, 166 MHz			240		mA
						7.5-ns cycle, 133 MHz			225		mA
						10-ns cycle, 100MHz			205		mA
ISB1		Automatic CE	VDD = Max, Device Deselected,			4-ns cycle, 250 MHz			120		mA
		Power-Down	VIN ≥ VIH or VIN ≤ VIL
						5-ns cycle, 200 MHz			110		mA
		Current—TTL Inputs	f = fMAX = 1/tCYC
						6-ns cycle, 166 MHz			100		mA
						7.5-ns cycle, 133 MHz			90		mA
						10-ns cycle, 100 MHz			80		mA
ISB2		Automatic CE	VDD = Max, Device Deselected,			All speeds			40		mA
		Power-down	VIN ≤ 0.3V or VIN > VDDQ – 0.3V, f = 0
		Current—CMOS
		Inputs

Notes:

10.Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).

11.TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

Document #: 38-05524 Rev. *F Page 7 of 15

[+] Feedback