Cypress CY7C1411BV18, CY7C1413BV18, CY7C1415BV18, CY7C1426BV18 CY7C1411BV18, CY7C1426BV18

CY7C1411BV18, CY7C1426BV18
CY7C1413BV18, CY7C1415BV18
Document Number: 001-07037 Rev. *D Page 2 of 30
Logic Block Diagram (CY7C1411BV18)
Logic Block Diagram (CY7C1426BV18)
1M x 8 Array
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
16
20
32
8
NWS[1:0]
VREF
Write Add. Decode
Write
Reg
16
A(20:0)
20
8
CQ
CQ
DOFF
Q[7:0]
8
8
8
Write
Reg Write Reg Write Reg
C
C
1M x 8 Array 1M x 8 Array 1M x 8 Array
8
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
20
36
9
BWS[0]
VREF
Write Add. Decode
Write
Reg
18
A(19:0)
20
9
CQ
CQ
DOFF
Q[8:0]
9
9
9
Write
Reg Write Reg Write Reg
C
C
1M x 9 Array 1M x 9 Array 1M x 9 Array 1M x 9 Array
9
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