Cypress CY7C1411BV18 manual Logic Block Diagram CY7C1413BV18, Logic Block Diagram CY7C1415BV18

CY7C1411BV18, CY7C1426BV18

CY7C1413BV18, CY7C1415BV18

Logic Block Diagram (CY7C1413BV18)

18

D[17:0]

19Address

A(18:0) Register

K

K CLK

Gen.

DOFF

VREF		Control
WPS
		Logic
BWS
	[1:0]

Write Add. Decode

Write

Write

Write

Write

19

Address

A(18:0)

Reg

Reg

Reg

Reg

Register

512K x

512K x

512K x

512K x

Decode

18Array

18Array

18Array

18Array

ReadAdd.

Logic

C

Control

RPS

Read Data Reg.

C

CQ

72

36

CQ

18

Reg.

Reg.

18

18

36

18

Q[17:0]

Reg.

18

Logic Block Diagram (CY7C1415BV18)

36

D[35:0]

18Address

A(17:0) Register

K

K CLK

Gen.

DOFF

VREF		Control
WPS
		Logic
BWS
	[3:0]

Write Add. Decode

Write

Write

Write

Write

18

Address

A(17:0)

Reg

Reg

Reg

Reg

Register

256K x

256K x

256K x

256K x

Decode

36Array

36Array

36Array

36Array

ReadAdd.

Logic

C

Control

RPS

Read Data Reg.

C

CQ

144

72

CQ

36

Reg.

Reg.

36

36

72

36

Q[35:0]

Reg.

36

Document Number: 001-07037 Rev. *D Page 3 of 30

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