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Cypress CY7C144, CY7C145 Figure 10. Semaphore Read After Write Timing, Either Side, Figure 11. Semaphore Contention

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CY7C145, CY7C144

Document #: 38-06034 Rev. *D Page 10 of 21

Figure 10. Semaphore Read After Write Timing, Either Side[25]

Figure 11. Semaphore Contention[26, 27, 28]

Notes

25.CE = HIGH for the duration of the above timing (both write and read cycle).

26.I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH

27.Semaphores are reset (available to both ports) at cycle start.

28.If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.

Switching Waveforms (continued)

tSOP

tAA

SEM

R/W

I/O0

VALID ADDRESS VALID ADDRESS

tHD

DATAINVALID DATA OUT VALID

tOHA

A0−A2

tAW

tHA

tACE

tSOP

tSCE

tSD

tSA tPWE

tSWRD tDOE

WRITECYCLE READ CYCLE

MATCH

tSPS

A0L−A2L

MATCH

R/WL

SEML

A0R−A2R

R/WR

SEMR

[+] Feedback

Contents

Main CY7C145, CY7C144 8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY Features Logic Block Diagram Functional Description Document #: 38-06034 Rev. *D Page 2 of 21 Pin Configurations Figure 1. 68-Pin PLCC (Top View) Figure 2. 64-Pin PLCC (Top View) Notes 3. I/O8R on the CY7C145. 4. I/O8L on the CY7C145. Document #: 38-06034 Rev. *D Page 3 of 21 Pin Configurations (continued) 7C144-25 7C145-25 7C144-35 7C145-35 CY7C145, CY7C144 Maximum Ratings Operating Range Electrical Characteristics CY7C145, CY7C144 Electrical Characteristics Capacitance Switching Characteristics CY7C145, CY7C144 Switching Characteristics Document #: 38-06034 Rev. *D Page 8 of 21 Switching Waveforms Figure 5. Read Cycle No. 1 (Either Port Address Access) Figure 6. Read Cycle No. 2 (Either Port CE /OE Access) Figure 7. Read Timing with Port-to-Port Delay (M/S=L)[19, 20] Figure 8. Write Cycle No. 1: OE Three-State Data I/Os (Either Port)[21, 22, 23] Figure 9. Write Cycle No. 2: R/W Three-State Data I/Os (Either Port)[21, 23, 24] Figure 10. Semaphore Read After Write Timing, Either Side Figure 11. Semaphore Contention Figure 12. Read with BUSY (M/S=HIGH)[20] Figure 13. Write Timing with Busy Input (M/S=LOW) Figure 14. Busy Timing Diagram No. 1 (CE Arbitration)[29] Figure 15. Busy Timing Diagram No. 2 (Address Arbitration) CER Valid First: CEL Valid First: Left Address Valid First: Figure 16. Interrupt Timing Diagrams Left Side Sets INTR: Right Side Clears INTR: Right Side Sets INTL: Left Side Clears INTL: CY7C145, CY7C144 Architecture Functional Description Write Operation Read Operation Page Figure 17. Typical DC and AC Characteristics Ordering Information 8K x8 Dual-Port SRAM 8K x9 Dual-Port SRAM Page Page Document History Page Sales, Solutions and Legal Information Worldwide Sales and Design Support Products PSoC Solutions