CY7C145, CY7C144

Document #: 38-06034 Rev. *D Page 3 of 21

Figure 3. 80-Pin TQFP

Pin Configurations (continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
16
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
37
36
38
39
40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
44
45
43
42
41
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
64
65
63
62
61
/O2L
/O3L
/O4L
/O5L
/O6L
/O7L
VCC
GND
/O0R
/O1R
2R
/O3R
/O4R
5R
GND
VCC
VCC
OEL
I/O0L
I/O8L
A5L
A12L
A11L
A10L
A9L
A8L
A7L
A6L
CEL
SEML
R/WL
A4L
A3L
A2L
A1L
A0L
GND
BUSYL
M/S
A0R
A1R
A2R
A3R
A4R
INTL
GND
OER
/O6R
A12R
A11R
A10R
A9R
A8R
A7R
A6R
NC
CER
SEMR
R/WR
CY7C145
BUSYR
INTR
I/O8R
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A5R
I/O7R
NC
/O
O
NC
I/O1L

Table 1. Pin Definitions

Left Port Right Port Description

I/O0L−7L(8L) I/O0R−7R(8R) Data bus Input/Output

A0L−12L A0R−12R Address Lines

CELCERChip Enable

OELOEROutput Enable

R/WLR/WRRead/Write Enable

SEML SEMRSemaphore Enable. When asserted LOW, allows access to eight semaphores. The three least signif-

icant bits of the address lines will determine which semaphore to write or read. The I/O0 pin is used

when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location.

INTLINTRInterrupt Flag. INTL is set when right port writes location 1FFE and is cleared when left port reads

location 1FFE. INTR is set when left port writes location 1FFF and is cleared when right port reads

location 1FFF.

BUSYLBUSYRBusy Flag

M/S Master or Slave Select

VCC Power

GND Ground

Table 2. Selection Guide

Description 7C144-15

7C145-15

7C144-25

7C145-25

7C144-35

7C145-35

7C144-55

7C145-55 Unit

Maximum Access Time 15 25 35 55 ns

Maximum Operating Current 220 180 160 160 mA

Maximum Standby Current for ISB1 60 40 30 30 mA

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