Contents
    
Main              
72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18                
Features
Configurations                
Functional Description
              CY7C1511KV18, CY7C1526KV18
Document Number: 001-00435 Rev. *E Page 2 of 31                
Logic Block Diagram (CY7C1511KV18)
Logic Block Diagram (CY7C1526KV18)              
CY7C1513KV18, CY7C1515KV18
Document Number: 001-00435 Rev. *E Page 3 of 31                
Logic Block Diagram (CY7C1513KV18)
Logic Block Diagram (CY7C1515KV18)              
Pin Configuration 
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout              
CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18
Pin Configuration                 
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
              CY7C1511KV18, CY7C1526KV18
Pin Definitions               
CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18
NC NC                
Pin Definitions 
              CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18
Functional Overview                
Read Operations
Write Operations                
Byte Write Operations
              Single Clock Mode
Concurrent Transactions                
Depth Expansion
Programmable Impedance                
Echo Clocks
              Application Example
Truth Table                
SRAM #4
SRAM #1                
BUS MASTER (CPU or ASIC)
              CY7C1511KV18, CY7C1526KV18
            Page
              CY7C1513KV18, CY7C1515KV18
IEEE 1149.1 Serial Boundary Scan (JTAG)                
Disabling the JTAG Feature
Test Access PortTest Clock                
Test Mode Select (TMS)
            Page
              CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18
TAP Controller State Diagram              
TAP Controller Block Diagram
TAP Electrical Characteristics               
TAP AC Switching Characteristics 
TAP Timing and Test Conditions              
CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18
Identification Register Definitions                 
Scan Register Sizes 
Instruction Codes              
Boundary Scan Order 
              Power Up Sequence in QDR-II SRAM
VV                
Power Up Sequence
PLL Constraints                
/
              Maximum Ratings
Operating Range                
Electrical Characteristics 
DC Electrical Characteristics                 
AC Electrical Characteristics 
              Electrical Characteristics 
DC Electrical Characteristics               
Capacitance
Thermal Resistance            
Page
              Switching Characteristics 
              CY7C1511KV18, CY7C1526KV18
Switching Waveforms                
READ READWRITE WRITE
12345                
67
              Ordering Information 
            Page
            Page
Document Number: 001-00435 Rev. *E Page 30 of 31              
Package Diagram
[+] Feedback                 
SOLDERPAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
1.40MAX.                
Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180
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