Cypress CY7C1511KV18, CY7C1513KV18, CY7C1515KV18, CY7C1526KV18 Switching Characteristics

CY7C1511KV18, CY7C1526KV18
CY7C1513KV18, CY7C1515KV18
Document Number: 001-00435 Rev. *E Page 25 of 31
Output Times
tCO tCHQV C/C Clock Rise (or K/K in single
clock mode) to Data Valid
– 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
tDOH tCHQX Data Output Hold after Output C/C
Clock Rise (Active to Active)
–0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns
tCCQO tCHCQV C/C Clock Rise to Echo Clock Valid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
tCQOH tCHCQX Echo Clock Hold after C/C Clock
Rise
–0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns
tCQD tCQHQV Echo Clock High to Data Valid 0.25 0.27 0.30 0.35 0.40 ns
tCQDOH tCQHQX Echo Clock High to Data Invalid –0.25 – –0.27 – –0.30 – –0.35 – –0.40 – ns
tCQH tCQHCQL Output Clock (CQ/CQ) HIGH [25] 1.25 – 1.4 – 1.75 – 2.25 – 2.75 – ns
tCQHCQHtCQHCQHCQ Clock Rise to CQ Clock Rise
(rising edge to rising edge) [25] 1.25 – 1.4 – 1.75 – 2.25 – 2.75 – ns
tCHZ tCHQZ Clock (C/C) Rise to High-Z
(Active to High-Z) [26, 27]
– 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
tCLZ tCHQX1 Clock (C/C) Rise to Low-Z [26, 27] –0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns
PLL Timing
tKC Var tKC Var Clock Phase Jitter – 0.20 – 0.20 – 0.20 – 0.20 – 0.20 ns
tKC lock tKC lock PLL Lock Time (K, C) 20–20–20–20–20–μs
tKC Reset tKC Reset K Static to PLL Reset 30 30 30 30 30 ns
Switching Characteristics (continued)
Over the Operating Range [22, 23]
Cypress
Parameter
Consortium
Parameter Description
333 MHz 300 MHz 250 MHz 20 0 MHz 167 MHz
Unit
Min Max Min Max Min Max Min Max Min Max
Notes
25.These parameters are extrapolated from the input timing parameters (tCYC/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
design and are not tested in production
26.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 100 mV from steady-state voltage.
27.At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
[+] Feedback