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Cypress CY7C1511KV18, CY7C1513KV18, CY7C1515KV18, CY7C1526KV18 CY7C1511KV18, CY7C1526KV18

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CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Document Number: 001-00435 Rev. *E Page 26 of 31

Switching Waveforms

Figure 5. Read/Write/Deselect Sequence [28, 29, 30]

12345

67

RPS

WPS

READ READWRITE WRITE

NOP NOP

DON’T CARE UNDEFINED

A0 A1

tKH tKHKH

tKL tCYC

ttHC

tSA tHA

SC tt

HCSC

tKHCH

tCQD

tCLZ

DOH

tCHZ

ttKL

tCYC

tCCQO

tCQOH

KHKH KH

Q00 Q03

Q01 Q02 Q20 Q23

Q21 Q22

tCO tCQDOH

tCQH tCQHCQH

D10 D11 D12 D13

tSD

tHD

tSD

tHD

D30 D31 D32 D33

Notes

28.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.

29.Outputs are disabled (High-Z) one clock cycle after a NOP.

30.In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note

applies to the whole diagram.

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Contents

Main 72-Mbit QDR-II SRAM 4-Word Burst Architecture CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Features Configurations Functional Description CY7C1511KV18, CY7C1526KV18 Document Number: 001-00435 Rev. *E Page 2 of 31 Logic Block Diagram (CY7C1511KV18) Logic Block Diagram (CY7C1526KV18) CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *E Page 3 of 31 Logic Block Diagram (CY7C1513KV18) Logic Block Diagram (CY7C1515KV18) Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1511KV18, CY7C1526KV18 Pin Definitions CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 NC NC Pin Definitions CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Functional Overview Read Operations Write Operations Byte Write Operations Single Clock Mode Concurrent Transactions Depth Expansion Programmable Impedance Echo Clocks Application Example Truth Table SRAM #4 SRAM #1 BUS MASTER (CPU or ASIC) CY7C1511KV18, CY7C1526KV18 Page CY7C1513KV18, CY7C1515KV18 IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Page CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Identification Register Definitions Scan Register Sizes Instruction Codes Boundary Scan Order Power Up Sequence in QDR-II SRAM VV Power Up Sequence PLL Constraints / Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics AC Electrical Characteristics Electrical Characteristics DC Electrical Characteristics Capacitance Thermal Resistance Page Switching Characteristics CY7C1511KV18, CY7C1526KV18 Switching Waveforms READ READWRITE WRITE 12345 67 Ordering Information Page Page Document Number: 001-00435 Rev. *E Page 30 of 31 Package Diagram [+] Feedback SOLDERPAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40MAX. Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions Document History Page