2K x 8 Reprogrammable PROM

CY7C291A

CY7C292A/CY7C293A

CypressSemiconductor Corporation • 3901North FirstStreet • SanJose • CA 95134 • 408-943-2600
March 1986 – Revised May 1993
92A

Features

•Windowed for reprogrammability
•CMOS for optimum speed/power
•High speed
—20 ns (commercial)
—25 ns (military)
•Low power
—660 mW (commercial and military)
•Low standby power
—220 mW (commercial and military)
•EPROM technology 100% programmable
•Slim 300-mil or standard 600-mil packaging available
•5V ±10% VCC, commercial and military
•TTL-compatible I/O
•Direct replacement for bipolar PROMs
•Capable of withstanding >2001V static discharge

Functional Description

The CY7C291A, CY7C292A, and CY7C293A are high-perfor-
mance 2K-word by 8-bit CMOS PROMs. They are functionally
identical, but are packaged in 300-mil (7C291A, 7C293A) and
600-mil wide plastic and hermetic DIP packages (7C292A).
The CY7C293A has an automatic power down feature which
reduces the power consumption by over 70% when deselect-
ed. The 300-mil ceramic package may be equipped with an
erasure window; when exposed to UV light the PROM is
erased and can then be reprogrammed. The memory cells uti-
lize proven EPROM floating-gate technolog y and b yte-wide in-
telligent programming algorithms.
The CY7C291A, CY7C292A, and CY7C293A are plug-in re-
placements for bipolar devices and offer the advantages of
lower power, reprogrammability, superior performance and
programming yield. The EPROM cell requires only 12.5V for
the supervoltage and low current requirements allow for gang
programming. The EPROM cells allow for each memory loca-
tion to be tested 100%, as each location is written into, erased,
and repeatedly exercised prior to encapsulation. Each PROM
is also tested for AC performance to guarantee that after cus-
tomer programming the product will meet DC and AC specifi-
cation limits.
A read is accomplished by placing an active LOW signal on
CS1, and active HIGH signals on CS2 and CS3. The contents
of the memory location addressed by the address line (A0 −
A10) will become available on the output lines (O0 − O7).

LogicBlock Diagram Pin Configurations

C291A-1
C291A-2
C291A-3
O7
O6
O5
O4
O3
O2
O1
O0
PROGRAM-
MABLE
ARRAY
MULTI-
PLEXER
GND
1
2
3
4
5
6
7
8
9
10
11 14
15
16
20
19
18
17
21
24
23
22
A6
A5
A4
A3
A2
A1
A0
O0
A7
O3
VCC
A8
A9
A10
O7
O6
O5
O4
CS1
O212 13
O1
CS3
CS2
28
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
1112 19
A5
V
CC
GND A6
A7
O3
O1
O018
O4
O5
NC
A0
A4
A3
A10
NC
A8
A9
NC
NC
CS1
CS2
O7
O6
A2
A1CS3
O2
CS1
CS2
CS3
POWER
DOWN
7C293A
Window available on
7C291Aand 7C293A
only.
DIP LCC/PLCC (Opaque Only)
Top Vi ew Top View
ADDRESS
DECODER
A0
A1
A2
A3
A4
A5
A6
A8
A9
A10
A7
COLUMN
ADDRESS
ROW
ADDRESS
7C291A
7C292A
7C293A 7C291A
7C293A