STK16C88-3

Software Controlled STORE/RECALL Cycle

 

 

 

 

The software controlled STORE/RECALL cycle follows. [11, 12]

 

 

 

 

 

Parameter

 

Alt

 

Description

 

35 ns

Unit

 

 

 

Min

 

Max

 

 

 

 

 

 

 

 

tRC

tAVAV

 

STORE/RECALL Initiation Cycle Time

35

 

 

ns

t

[11]

t

AVEL

 

Address Setup Time

0

 

 

ns

 

SA

 

 

 

 

 

 

 

tCW[11]

tELEH

 

Clock Pulse Width

25

 

 

ns

tHACE[7, 11]

tELAX

 

Address Hold Time

20

 

 

ns

tRECALL

 

 

 

RECALL Duration

 

 

20

μs

Switching Waveforms

Figure 10. CE Controlled Software STORE/RECALL Cycle [12]

ADDRESS

CE

OE

DQ (DATA)

tRC

ADDRESS # 1

tSA

 

 

 

tSCE

 

 

tHACE

DATA VALID

tRC

ADDRESS # 6

tSTORE / tRECALL

HIGH IMPEDANCE

DATA VALID

Notes

11.The software sequence is clocked on the falling edge of CE without involving OE (double clocking will abort the sequence).

12.The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.

Document Number: 001-50594 Rev. **

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Cypress STK16C88-3 manual Software Controlled STORE/RECALL Cycle, Parameter Alt Description 35 ns Unit Min