STK16C88-3
Document Number: 001-50594 Rev. ** Page 8 of 14
AC Switching Characteristics
SRAM Read Cycle
Parameter Description 35 ns Unit
Min Max
Cypress
Parameter Alt
t
ACE
t
ELQV
Chip Enable Access Time 35 ns
t
RC [5]
t
AVAV,
t
ELEH
Read Cycle Time 35 ns
t
AA [6]
t
AVQV
Address Access Time 35 ns
t
DOE
t
GLQV
Output Enable to Data Valid 15 ns
t
OHA [6]
t
AXQX
Output Hold After Address Change 5 ns
t
LZCE [7]
t
ELQX
Chip Enable to Output Active 5 ns
t
HZCE [7]
t
EHQZ
Chip Disable to Output Inactive 13 ns
t
LZOE [7]
t
GLQX
Output Enable to Output Active 0 ns
t
HZOE [7]
t
GHQZ
Output Disable to Output Inactive 13 ns
t
PU [4]
t
ELICCH
Chip Enable to Power Active 0 ns
t
PD [3, 4]
t
EHICCL
Chip Disable to Power Standby 35 ns
Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled
[5, 6]
Figure 6. SRAM Read Cycle 2: CE and OE Controlled
[5]
W
5&
W
$$
W
2+$
$''5(66
'4'$7$287 '$7$9$/,'
$''5(66
W
5&
&(
W
$&(
W
/=&(
W
3'
W
+=&(
2(
W
'2(
W
/=2(
W
+=2(
'$7$9$/,'
$&7,9(
67$1'%<
W
38
'4'$7$287
,&&
Notes
5. WE must be HIGH during SRAM Read Cycles.
6. I/O state assumes CE and OE < V
IL
and WE > V
IH
; device is continuously selected.
7. Measured ±200 mV from steady state output voltage.
[+] Feedback