3.3V, 125-MHz, Multi-Output Zero Delay Buffer
Z9973
CypressSemiconductor Corporation • 3901North FirstStreet • SanJose • CA 95134 • 408-943-2600
Document #: 38-07089 Rev. *D Revised December 21, 2002

Features

• Output frequency up to 125 MHz
• 12 clock outputs: frequency configurable
• 350 ps max output-to-output skew
• Configurable output disable
• Two reference clock inputs for dynamic toggling
• Oscillator or PECL reference input
• Spread spectrum-compatible
• Glitch-free output clocks transitioning
• 3.3V power supply
• Pin-compatible with MPC973
• Industrial temperature range: –40°C to +85°C
• 52-pin TQFP package
Note:1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz.
.
Table 1. Frequency Table[1]
VC0_SEL FB_SEL2 FB_SEL1 FB_SEL0 FVC0
00008x
000112x
001016x
001120x
010016x
010124x
011032x
011140x
10004x
10016x
10108x
101110x
11008x
110112x
111016x
111120x

Block Diagram Pin Configuration

REF_SEL
0
1
0
1
Phase
Detector VCO
LPF
Sync
Frz
DQQA0
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
0
1
/2
Power-On
Reset
Output Disable
Circuitry
Data Generator
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10
Sync Pulse
PECL_CLK
PECL_CLK#
TCLK0
TCLK1
TCLK_SEL
FB_IN
FB_SEL2
MR#/OE
SELA(0,1) 2
SELB(0,1) 2
SELC(0,1) 2
FB_SEL(0,1) 2
SCLK
SDATA
INV_CLK
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
FB_OUT
SYNC
12
VCO_SEL
PLL_EN
VSS
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
PECL_CLK
PECL_CLK#
VDD
FB_SEL1SYNC
VSS
QC0
VDDC
QC1SELC0SELC1QC2
VDDC
QC3
VSS
INV_CLKSELB1SELB0SELA1SELA0QA3
VDDC
QA2
VSS
QA1
VDDC
QA0
VSS
VCO_SEL
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
QB3
FB_IN
VSS
FB_OUT
VDDC
FB_SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40

Z9973

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