Hot Swap: Timing Considerations
10006024-04 Katana®752i User’s Manual 12-5
low (active). This occurs when power supply voltages are not within the proper tolerance or
when the BDSEL* signal is not driven low (active) to the Hot Swap controller. The LED
remains illuminated until software clears bit 0 at address F821,000616 in the HSL PLD.
2When the operator locks the ejector handle, the MV64460 bridge chip senses the event
and notifies the software that a board has been inserted. It also drives ENUM on the cPCI
backplane when the switch is closed (until cleared by software).
The Hot Swap logic functions as follows when a board is removed from a slot:
1The operator opens the ejector handle (but does not yet remove the board from the slot),
and the MV64460 bridge chip senses the event.
2The REM bit in the Hot Swap Status and Control register (HS_CSR) is set and the
PCI0_ENUMn pin on the MV64460 is asserted.
3The software identifies the board to be extracted and clears the REM bit by writing a one to
it.
4The MV64460 deasserts the PCI0_ENUMn pin and the processor (750GL) performs board
quiescence tasks.
5Once the board is properly shut down, the processor illuminates the Hot Swap LED by
writing a one to bit 0 at address F821,000616 in the HSL PLD. This indicates that the board
can be removed safely from the system.

TIMING CONSIDERATIONS

The Katana®752i complies with Configuration 2 of the PCI Telecom Mezzanine/Carrier Card
Specification, PICMG 2.15. It is an initially-retrying board, which means that from the time of
insertion and/or cPCI RST negation, the Katana®752i will assert ENUM and retry all incom-
ing cPCI configuration cycles until the board is minimally initialized. The time delay associ-
ated with this functionality is approximately 300 milliseconds. Once this time has expired,
the Katana®752i will respond to cPCI configuration cycles.
In addition to this retry delay, the Katana®752i requires approximately another five sec-
onds to initialize all on-card DRAM before it can support cPCI memory cycles. Accessing the
Katana®752i on-card DRAM memory within five seconds may result in ECC errors or incor-
rect data. Please refer to “Power-Up Timing” on page15-5 for more details.