Emerson 752I Hardware Implementation Dependent 2 Register

Processor: Processor Initialization

10006024-04 Katana®752i User’s Manual 4-7

PR0: PLL0 Range select bits.

PC1: PLL1 Configuration bits.

PRI: PLL1 Range bits.

Hardware Implementation Dependent 2 Register

Parity is implemented for the following arrays: I-Cache, I-Tag, D-Cache, D-Tag, and L2 Tag.

Status bits are set when a parity error is detected and cleared when the HID2 register is

written.

Register 4-3: 750GL Hardware Implementation Dependent, HID2

STMUMD: Disable store miss-under-miss processing.

FICBP: Force I-Cache bad parity.

FITBP: Force I-Tag bad parity.

FDCBP: Force D-Cache bad parity.

FDTBP: Force D-Tag bad parity.

FL2TBP: Force L2-Tag bad parity.

ICPS: L1 I-Cache/I-Tag Parity Error Status/Mask.

DCPS: L1 D-Cache/D-Tag Parity Error Status/Mask.

L2PS: L2 Tag Parity Error Status/Mask.

ICPE: L1 I-Cache/I-Tag Parity checking Enable.

DCPE: L1 D-Cache/D-Tag Parity checking Enable.

L2PE: L2 Tag Parity checking Enable.

0234 15

Reserved

STMUMD

Reserved

1

6

1

920 2122 23 24 25262728293031

Reserved FICBP

FITBP FDCBP FDTBP

FL2TBP

ICPS

DCPS

L2PS Res. ICPE

DCPE L2PE

Contents

Main Page Regulatory Agency Warnings & Notices FCC RULES AND REGULATIONS PART 15 EMC COMPLIANCE EC Declaration of Conformity Contents 1Overview 2Setup 3 Reset Logic 4Processor 8Local PCI Bus 9 PTMC Interface 10Ethernet Interfaces 11IPMI Controller 12Hot Swap Contents 16Acronyms Page Figures Page Tables Tables Registers Page Section 1 Overview COMPONENTS AND FEATURES Page Page Overview: 1-4 FUNCTIONAL OVERVIEW PTMCEthernet CT Bus ADDITIONAL INFORMATION Product Certification RoHS Compliance Terminology and Notation Technical References Page Device/Interface:Type: Document: Device/Interface:Type: Document: Page Section 2 Setup ELECTROSTATIC DISCHARGE KATANA752I CIRCUIT BOARD Figure 2-1: Katana752i Front Panel 10006024-04 Katana752i Users Manual 2-3 Figure 2-2: Component Map, Top (Rev. 03) LP1 J22 PMC Site #2 J7 U10 Figure 2-3: Component Map, Bottom (Rev. 03) CR17 C761 R872 R884 Figure 2-4: Jumper, Fuse, and Switch Locations, Top 2-6 Figure 2-5: Fuse, and LED Locations, Bottom CR17 C761 R872 R884 Identification Numbers Connectors Fuses LEDs Setup: LED: Color: Signal Name: Comments: KATANA752I SETUP Setup: Power Requirements Environmental Requirements TROUBLESHOOTING Setup: moninit <four-digit board serial number> noburn Technical Support Product Repair Page Section 3 Reset Logic GENERAL OVERVIEW Reset Logic: 3-2 Figure 3-1: Katana752i Reset Diagram 3. Zircon PM powered from IPMI power 2. PLD powered from early power Reset Logic: RESET SOURCES CompactPCI Reset Enable Power Monitor 750GL Processor Reset Reset Logic: Device Bus PLD GL Section 4 Processor PROCESSOR OVERVIEW Features Processor: Figure 4-1: 750GL Block Diagram Physical Memory Map Processor: Figure 4-2: 750GL Memory Map Processor: PROCESSOR RESET PROCESSOR INITIALIZATION Hardware Implementation Dependent 0 Register Hardware Implementation Dependent 1 Register Hardware Implementation Dependent 2 Register Processor: EXCEPTION HANDLING Exception: Vector Address Hex Offset: Notes: Processor: EXCEPTION PROCESSING Page Processor: CACHE MEMORY L1 Cache L2 Cache Page Processor: JTAG/COP HEADERS Pin: Signal: I/O: Description: Page Section 5 System Controller OVERVIEW System Controller: CPU INTERFACE System Controller: SDRAM CONTROLLER DEVICE CONTROLLER INTERFACE System Controller: INTERNAL (IDMA) CONTROLLER TIMER/COUNTERS PCI INTERFACE PCI Configuration Space System Controller: PCI Identification PCI Read/Write PCI Interface Registers System Controller: DOORBELL REGISTERS Outbound Doorbells Inbound Doorbells WATCHDOG TIMER System Controller: ON-CARD MEMORY User Flash SDRAM System Controller: EEPROMs I2C INTERFACE System Controller: 10006024-04 Katana752i Users Manual 5-9 Figure 5-2: I2C Interface Diagram System Controller: GPIO SIGNAL DEFINITIONS Pin: Direction: Description: System Controller: Page Section 6 Device Bus PLD RESET REGISTERS Device Bus PLD: INTERRUPT REGISTERS Device Bus PLD: PRODUCT IDENTIFICATION PCI ENUMERATION Device Bus PLD: REVISION REGISTERS BOARD CONFIGURATION REGISTERS Page Device Bus PLD: OTHER REGISTERS Section 7 Real-Time Clock BLOCK DIAGRAM OPERATION Real-Time Clock: CLOCK OPERATION Real-Time Clock: Page Section 8 Local PCI Bus PCI ENUMERATION PCI ID SELECT AND INTERRUPTS Local PCI Bus: GEOGRAPHICAL ADDRESSING PCI BUS CONTROL SIGNALS Page Local PCI Bus: Section 9 PTMC Interface PTMC INSTALLATION PTMC Interface: PTMC CONNECTOR PINOUTS Pin J11 J12 J13 J14 Page Pin J21 J22 J23 J24 Section 10 Ethernet Interfaces ETHERNET ADDRESS Ethernet Interfaces: ETHERNET PORTS FRONT PANEL ETHERNET CONNECTOR PINOUTS Ethernet Interfaces: OPTIONAL RMII PHY DEVICES Ethernet Interfaces: Magnetics PHY 0x6 RMII Section 11 IPMI Controller SMB/IPMI OVERVIEW Page IPMI Controller: Figure 11-1: IPMB Connections Block Diagram IPMI Microcontroller IPMB (SCL, SDA, PWR) Katana752i IPMI Controller: I/O INTERFACE Zircon PM Pin: Signal Name: Function: IPMI Controller: I2C INTERFACES IPMI MESSAGE PROTOCOL Page IPMI Network Function Codes Hex Code Value(s): Name: Type: Description: IPMI Completion Codes Code: Description: Zircon PM IPMI Commands Get Sensor Reading (Sensor/Event) Page Type: Byte: Data Field: (continued) Master Write-Read I2C (Application) Write Setting (OEM) Read Setting (OEM) Set Heartbeat (OEM) Get Heartbeat (OEM) IPMI FRU Information Item: Description: IPMI Device SDR Repository IPMI Event Messages Page Page Section 12 Hot Swap HOT SWAP LOGIC (HSL) PLD Hot Swap: CPCI FUNCTIONALITY HOT SWAP LED AND EJECTOR SWITCH CONTROL cPCI Hot Swap Page Hot Swap: Non-cPCI Hot Swap Hot Swap: TIMING CONSIDERATIONS Hot Swap: HEALTHY* SIGNAL Section 13 CT Bus Interface PICMG 2.15 CONFIGURATION 2 CT Bus Interface: KATANA752I CT BUS OPTIONS CLOCKING CT Bus Interface: SIGNAL CONTROL CT Bus Interface: CT BUS ROUTING WITHOUT THE T8110 (OPTION 1) CT Bus Interface: Figure 13-2: CT Signal Routing Diagram T8110 Not Installed (option 1) Katana750i CT BUS ROUTING WITH THE T8110 INSTALLED (OPTION 2) T8110: PTMC Site 1: PTMC Site 2: Local CT Bus Operation Figure 13-3: CT Signal Routing Diagram T8110 Installed (option 2) H.110 CT Bus Operation Fig.13-3 and Fig. 13-1. Section 14 Backplane Signals OVERVIEW PINOUTS Page Pin: Row A: Row B: Row C: Row D: Row E: Row F: Pin: Row A: Row B: Row C: Row D: Row E: Row F: Page Section 15 Monitor COMMAND-LINE FEATURES Monitor: BASIC OPERATION Power-Up/Reset Sequence 15-4 Figure 15-2: Power-up/Reset Sequence Flowchart Power-Up Timing POST Diagnostic Results Monitor SDRAM Usage Monitor: MONITOR RECOVERY AND UPDATES Recovering the Monitor Updating the Monitor via TFTP Monitor: Resetting Environment Variables MONITOR COMMAND REFERENCE Command Syntax Command Help Typographic Conventions BOOT COMMANDS bootbus bootcrc bootd bootelf bootm bootp bootv bootvx rarpboot tftpboot Page Monitor: cmp cp find md Monitor: mm nm mw Monitor: FLASH COMMANDS cp erase flinfo Monitor: protect EEPROM / I2C COMMANDS eeprom Monitor: icrc32 iloop imd ipmifirmload Monitor: iprobe ETHERNET CONTROLLER EEPROM COMMANDS initeth4rom filleth4rom Monitor: envinit printenv saveenv setenv Monitor: Page frusetuser gethvr getmonver getpcimemsize getpcimode getphysloc getspr go help isdram loop memmap moninit pci reset run setpcimemsize setpcimode setspr script showmac showpci showtemp version The version command displays the monitors current version number. Definition: ENVIRONMENT VARIABLES Variable: Default Value: Description: Variable: Default Value: Description: (continued) Variable: Default Value: Description: (continued) Variable: Description: Monitor: Section 16 Acronyms Page Acronyms: Page Index A B C E Index N O P R Index S T U W Page Notes