RX − 8564 LC
13.1.9. CLKOUT output register (Reg - 0D [h])
Address [h] | Function | bit 7 | bit 6 | bit 5 | bit 4 | bit 3 | bit 2 | bit 1 | bit 0 |
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0D | CLKOUT frequency | FE | ⋅ | ⋅ | ⋅ | ⋅ | ⋅ | FD1 | FD0 |
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• This register is used to control clock output via the CLKOUT output pin.
• This register is valid only when the CLKOE input pin is at high level, at which time clock output is enabled or disabled (stopped) depending on the settings in this register.
∗ When the CLKOE input pin is at low level, CLKOUT is at low level regardless of the settings in this register.
1) FE bit ( Frequency output Enable )
When this register is valid (when CLKOE is at high level), it is used to control the CLKOUT pin's output status.
When the FE bit value is "1", the CLKOUT pin is in output mode. The content being output at that time is the frequency specified via the FD1 and FD0 bit.
When the FE bit value is "0", the CLKOUT pin is output STOP mode (= low level).
2) FD1, FD0 bits
A combination of the FD1 and FD0 bits is used to select the frequency to be output.
3) CLKOUT output based on various settings
CLKOE pin | FE | FD1 | FD0 | CLKOUT pin | ||
input | bit | bit | bit | output |
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| 0 | 0 | 32768 Hz Output | ( | |
" H " | 1 | 0 | 1 | 1024 Hz Output | ( | |
1 | 0 | 32 Hz Output | ( | |||
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| 1 | 1 | 1 Hz Output | ( | |
| 0 | Χ | Χ | OFF | ( " L " ) | |
" L " | 1 | Χ | Χ | OFF | ( " L " ) | |
0 | Χ | Χ | OFF | ( " L " ) | ||
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Χ : don't care |
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∗During initial
Consequently, 32.768 kHz output can be obtained from the CLKOUT output pin by setting the CLKOE input pin to high level.
Note) Re: CLKOUT output operation when STOP bit value is "1"
Note with caution that when the STOP bit value is "1", output via CLKOUT may be stopped, depending on the selected frequency.
(1)When 32.768 kHz output has been selected, output continues at 32.768 kHz.
(2)When any other frequency has been set (1024Hz, 32Hz, or 1Hz), CLKOUT output is stopped.
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