C141-E072-01ENxii
5.3 Protocol for command abort........................................................................................... 5 - 69
5.4 WRITE SECTOR(S) command protocol........................................................................ 5 - 70
5.5 Protocol for the command execution without data transfer ............................................5 - 71
5.6 Normal DMA data transfer............................................................................................. 5 - 73
5.7 Ultra DMA termination with pull-up or pull-down................................ ........................ 5 - 84
5.8 PIO data transfer timing.................................................................................................. 5 - 85
5.9 Multiword DMA data transfer timing (mode 2) .............................................................5 - 86
5.10 Initiating an Ultra DMA data in burst............................................................................. 5 - 87
5.11 Sustained Ultra DMA data in burst.................................................................................5 - 90
5.12 Host pausing an Ultra DMA data in burst ......................................................................5 - 91
5.13 Device terminating an Ultra DMA data in burst............................................................. 5 - 92
5.14 Host terminating an Ultra DMA data in burst.................................................................5 - 93
5.15 Initiating an Ultra DMA data out burst........................................................................... 5 - 94
5.16 Sustained Ultra DMA data out burst...............................................................................5 - 95
5.17 Device pausing an Ultra DMA data out burst................................................................. 5 - 96
5.18 Host terminating an Ultra DMA data out burst...............................................................5 - 97
5.19 Device terminating an Ultra DMA data out burst........................................................... 5 - 98
5.20 Power-on Reset Timing.................................................................................................. 5 - 99
6.1 Response to power-on................................ .................................................................... 6 - 2
6.2 Response to hardware reset ............................................................................................6 - 3
6.3 Response to software reset..............................................................................................6 - 4
6.4 Response to diagnostic command ..................................................................................6 - 5
6.5 Address translation (example in CHS mode).................................................................. 6 - 7
6.6 Address translation (example in LBA mode) .................................................................6 - 8
6.7 Sector slip processing..................................................................................................... 6 - 11
6.8 Alternate cylinder assignment ........................................................................................6 - 12
6.9 Data buffer configuration ...............................................................................................6 - 13