Fujitsu MPD3XXXAH C141-E072-01EN 5 - 89, Table 5.16 Ultra DMA data burst timing requirements (2 of 2)

C141-E072-01EN 5 - 89
Table 5.16 Ultra DMA data burst timing requirements (2 of 2)
NAME MODE 0
(in ns) MODE 1 (in ns) MODE 2 (in ns) MODE 3 (in ns) MODE 4 (in ns) COMMENT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX (see Notes 1 and 2)
tZIORDY 00000Minimum time before driving
IORDY
tACK 20 20 20 20 20 Setup and hold times for DMACK-
(before assertion or negation)
tSS 50 50 50 50 50 Time from STROBE edge to
negation of DMARQ or assertion of
STOP (when sender terminates a
burst)
Notes:
1) Unless otherwise specified, timing parameters shall be measured at the connector of the sender or receiver to which the parameter
applies (see Note 5 for exceptions). For example, the sender shall stop generating STROBE edges t
RFS after the negation of
DMARDY-. Both STROBE and DMARDY- timing measurements are taken at the connector of the sender.
2) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.
3) tUI, tMLI and tLI indicate sender-to-recipient or recipient-to-sender interlocks, i.e., one agent (either sender or recipient) is waiting for
the other agent to respond with a signal before proceeding. t
UI is an unlimited interlock that has no maximum time value. t MLI is a
limited time-out that has a defined minimum. t
LI is a limited time-out that has a defined maximun.
4) Special cabling shall be required in order to meet data setup (t
DS) and data hold (tDH) times in modes 3 and 4.
5) Timing for tDVS and tDVH shall be met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value.