HP c-Class Performance Tuning manual PCIe link width improperly negotiated

IMPORTANT: Some PCI Express chips do not properly report PCIe errors, or they might report errors when none exist. In most cases, this occurs on a bridge chip. This failure typically shows under the following conditions:

•Multiple rapid executions of the fio-pci-checkutility were issued.

•No data is passing over the bus reporting errors.

•All drivers for attached peripherals are unloaded.

Below is an example of PCI Express errors captured on a system with an IO Accelerator.

NOTE: Windows® operating systems do not allow clearing of all errors, so only errors registered on the IO Accelerators can be considered.

Root Bridge PCIe 3000 MB/sec

	Bridge 00:02.00 (09-12)
	Needed 1000 MB/sec Avail 1000 MB/sec
	Bridge 09:00.00 (0a-0f)
	Needed 1000 MB/sec Avail 1000 MB/sec
	* Fatal Error(s): Detected
`	* Unsupported Type(s): Detected
	Clearing Errors
	Bridge 0a:00.00 (0b-0d)

Needed 1000 MB/sec Avail 1000 MB/sec

ioDrive 0b:00.0 Firmware 14071

Bridge 00:04.00 (13-15)

Needed 1000 MB/sec Avail 1000 MB/sec

ioDrive 13:00.0 Firmware 14071

PCIe link width improperly negotiated

Issue

Currently shipping IO Accelerators are x4 PCI Express cards. If the system is having difficulties communicating with the IO Accelerator, the system might communicate with the IO Accelerator using only an x1 link, which has 1/4th the performance of an x4 link.

Solution

Use the fio-pci-checkutility to check for this problem and to report any issues with link width.

NOTE: The fio-pci-checkutility is not fully functional on all operating systems.

Below is an example of PCI link width errors captured on a system with an IO Accelerator.

Root Bridge PCIe 1750 MB/sec

Bridge 00:01.00 (01-01)

Needed 1000 MB/sec Avail 1000 MB/sec

Current control settings: 0x000f

Debugging performance issues 12