The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data) after the configuration phase has been activated by writing 55h to I/O port 2Eh. The desired interface (logical device) is initiated by firmware selecting logical device number of the 47B347 using the following sequence:
1.Write 07h to I/O register 2Eh.
2.Write value of logical device to I/O register 2Fh.
3.Write 30h to I/O register 2Eh.
4.Write 01h to I/O register 2Fh (this activates the interface). Writing AAh to 2Eh deactivates the configuration phase.
The systems covered in this guide utilize the following specialized functions built into the LPC SCH5317 I/O Controller:
■Power/Hard drive LED control—The I/O controller provides color and blink control for the front panel LEDs used for indicating system events (refer to Table 4-14).
■Intruder sensing—The battery-backed D-latch logic internal to the SCH5317 is connected to the hood sensor switch to record hood (cover) removal.
■Hood lock/unlock—Supported on SFF, ST, MT, and CMT form factors, logic internal to the SCH5317 controls the lock bar mechanism.
■I/O security—The parallel, serial, and diskette interfaces may be disabled individually by software and the SCH5317's disabling register locked. If the disabling register is locked, a system reset through a cold boot is required to gain access to the disabling (Device Disable) register.
■Processor present/speed detection—One of the battery-back general-purpose inputs (GPI26) of the SCH5317 detects if the processor has been removed. The occurrence of this event is passed to the ICH8 that will, during the next boot sequence, initiate the speed selection routine for the processor.
■Legacy/ACPI power button mode control—The SCH5317 receives the pulse signal from the system's power button and produces the PS On signal according to the mode (legacy or ACPI) selected. Refer to chapter 7 for more information regarding power management.
