4 BIOS overview

BIOS addresses

DMA channel controllers

Only “I/O-to-memory” and “memory-to-I/O” transfers are allowed. “I/O-to-I/O” and “memory-to-memory” transfers are disallowed by the hardware configuration.

The system controller supports seven DMA channels, each with a page register used to extend the addressing range of the channel to 16 MB. The following table summarizes how the DMA channels are allocated.

 

DMA controller

 

 

Channel

Function

 

 

0

Free

1

Free if not used for parallel port in Setup

2

Free

3

Free if not used for parallel port in Setup

4

Used to cascade DMA channels 0-3

5

Free

6

Free

7

Free

 

 

interrupt controllers

The Interrupt Requests (IRQ) are numbered sequentially, starting with the master controller, and followed by the slave.

 

IRQ

Interrupt Request Description

 

(Interrupt Vector)

 

 

 

 

 

 

 

INTR

 

 

 

 

 

 

IRQ0

System Timer

 

 

 

 

 

IRQ1

Keyboard Controller

 

 

 

 

 

IRQ3

3 COM LAN

 

 

 

 

 

IRQ4

Used by serial post if enabled - CON1

 

 

 

 

 

IRQ5

Audio AC’97

 

 

 

 

 

 

 

 

 

36