IBM 610, 6E1, 6C1 manual Architecture and technical overview

2

Chapter 2. Architecture and technical overview

The following sections provide more detailed information about the architecture of the Models 6C1 and 6E1. Figure 2-1shows the high level system block diagram of both models.

Processor Card
	4 MB L2
POWER3-II	w/ 375 MHz
	250 MHz
375 MHz	w/ 375 MHz
or	225 MHz
450 MHz	w/ 450 MHz
	8 MB L2
	w/ 450 MHz

Processor Card
	4 MB L2
POWER3-II	w/ 375 MHz
	250 MHz
375 MHz	w/ 375 MHz
or	225 MHz
450 MHz	w/ 450 MHz
	8 MB L2
	w/ 450 MHz

			Addr/Cntl			6xx Data Bus 16 Bytes @ 93.75 MHz w/ 375				MHz
					6xx Address Bus		16 Bytes @ 90 MHz w/ 450 MHz
						16 Bytes @ 93.75 MHz w/ 375 MHz
	Memory									Data
	Address				Memory Data Bus	16 Bytes @ 90 MHz w/ 450 MHz
								6xx-MX Bus
			Memory						66 MHz
											System Planar
		512 MB - 8 GB
I/O Planar
			Integrated Service
				Processor

PCI Bridge

PCI Bridge

ISA Bridge

3rd serial	Super	IDE	10/100	10/100
port	I/O	CD-	Ethernet	Ethernet
		ROM

SCSI Controller

Internal	External
Ultra3-SCSI	Ultra3-SCSI

2 PCI Slots

32bit 33 MHz 5v

1 PCI Slots

64bit

33MHz

5v

2 PCI Slots

64-bit

50MHz 3.3v

Figure 2-1 Model 6C1 and 6E1 - high-level system block diagram

© Copyright IBM Corp. 2001 9