![Chapter 2. Architecture and technical overview](/images/new-backgrounds/110772/11077233x1.webp)
2
Chapter 2. Architecture and technical overview
The following sections provide more detailed information about the architecture of the Models 6C1 and 6E1. Figure
Processor Card | |
| 4 MB L2 |
w/ 375 MHz | |
| 250 MHz |
375 MHz | w/ 375 MHz |
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or | 225 MHz |
450 MHz | w/ 450 MHz |
8 MB L2 | |
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Processor Card | |
| 4 MB L2 |
w/ 375 MHz | |
| 250 MHz |
375 MHz | w/ 375 MHz |
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or | 225 MHz |
450 MHz | w/ 450 MHz |
8 MB L2 | |
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| Addr/Cntl |
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| 6xx Data Bus 16 Bytes @ 93.75 MHz w/ 375 | MHz | |||||||||||||||
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| 6xx Address Bus |
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| 16 Bytes @ 93.75 MHz w/ 375 MHz |
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| Data |
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| Memory Data Bus | 16 Bytes @ 90 MHz w/ 450 MHz |
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| Memory |
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| System Planar | ||||||||||
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| 512 MB - 8 GB |
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I/O Planar |
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| Integrated Service |
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| Processor |
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PCI Bridge
PCI Bridge
ISA Bridge |
3rd serial | Super | IDE | 10/100 | 10/100 | |
port | I/O | CD- | Ethernet | Ethernet | |
ROM | |||||
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SCSI Controller
Internal |
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2 PCI Slots
32bit 33 MHz 5v
1 PCI Slots
64bit
33MHz
5v
2 PCI Slots
50MHz 3.3v
Figure 2-1 Model 6C1 and 6E1 - high-level system block diagram
© Copyright IBM Corp. 2001 | 9 |