IBM 6C1 System bus, PCI-bus, slots, and adapters, Memory boot time deconfiguration, Bus bandwidth

2.2.1 Memory boot time deconfiguration

Memory boot time deconfiguration is a function implemented in the service processor firmware for removing a memory segment or DIMM from the system configuration at boot time. The objective is to minimize system failures or data integrity exposure due to faulty memory hardware. The memory segment or DIMM that is deconfigured remains offline for subsequent reboots until the faulty memory hardware is replaced. This function provides the option for the user to manually deconfigure or re-enable a previously deconfigured memory segment or DIMM using the Service Processor menu.

Memory can also be decreased with AIX using the rmss command. This is useful for certain benchmark simulations.

Note: Memory cards can physically be removed only when the power is turned off to the entire system.

2.2.2 Memory interchange with other systems

The 2x256 MB DIMMs (# 4120) or 2x512 MB DIMMs (# 4121) options can be interchanged with the RS/6000® Models 44P-170, 44P-270, and the IBM ^pSeries 640 Model B80.

2.3 System bus

The 6XX bus or system bus is optimized for high-performance and multiprocessing performance. The bus is fully parity checked and each memory or cache request is range checked and positively acknowledged for error detection. Any error will cause a machine check condition and is logged in the AIX error log. The system bus speed is operated at 93.75 MHz with the 375 MHz processor card (1:4 ratio), and at 90 MHz with the 450 MHz processor card (1:5 ratio).

2.3.1 Bus bandwidth

The following are the theoretical maximum bandwidths, as applicable for an 2-way 450 MHz SMP configuration:

￿Memory bandwidth: 1.44 GB/s

￿Processor bandwidth: 1.44 GB/s

￿Bandwidth of the PowerPC® 6xx bus used to the I/O interface: 528 MB/s

2.4PCI-bus, slots, and adapters

The IBM ^pSeries 610 Models 6C1 and 6E1 are compliant with Revision 2.1 of the peripheral component interconnect (PCI) specifications and implement two peer PCI busses:

a32-bit data bus operating at 33 MHz and a 64-bit bus operating at 50 MHz. There are five PCI slots available. Slots one and two are 64-bit capable and can run up to speeds of 50 MHz. Slot three is 64-bit capable, and slots four and five are 32-bit. Slots three, four, and five run at 33 MHz.

A variety of graphics, SCSI, Fibrechannel, LAN, WAN, asynchronous, and SSA adapter cards can be installed in the Models 6C1 and 6E1.

14pSeries 610 Models 6C1 and 6E1 Technical Overview and Introduction