IBM 970MP - page 12

Application Note
(Includes Differences for 970FX to 970MP)
IBM PowerPC® 970MP RISC Microprocessor Preliminary
5. Design Enhancements for PowerPC 970MP
Page 12 of 25
AppNote_970FX-MP_Differences_Body.fm.1.0
November 15, 2006
5.1.1 1MB L2 Cache per Core
The 970MP L2 cache design doubles the cache array size and capacity from 970FX, with a corresponding
doubling in size of the two copies of the L2 tag arrays. Like the 970FX, it is an 8-way set associative cache of
128 B lines, but now consists of 1024 sets. The latency for L1 misses that hit in the L2 is increased by two
processor cycles in the 970MP, due to the longer path from the core to the larger L2 array. This load-use
penalty for fixed-point unit operands that hit in the 1 MB L2 cache is 14 processor cycles.